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LGDP4531
Rev 1.15
LGDP4531
720-Channel, 262,144-Color One-Chip Driver with RAM, Power Supply and Gate Circuits for Amorphous TFT-LCD Panels
Rev 1.15 2007-7-3
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Description ...................................................................................................................................................4 Features ........................................................................................................................................................5 Block Diagram .............................................................................................................................................6 Pin Function .................................................................................................................................................7 PAD Arrangement.....................................................................................................................................11 PAD Coordinate ........................................................................................................................................12 Bump Arrangement ....................................................................................................................................18 Block Function ...........................................................................................................................................19 System Interface ....................................................................................................................................19 External Display Interface .....................................................................................................................19 Address Counter (AC) ...........................................................................................................................20 Graphics RAM (GRAM) .......................................................................................................................20 Grayscale Voltage Generating Circuit ...................................................................................................20 Timing Generator ..................................................................................................................................20 Oscillator (OSC) ....................................................................................................................................20 LCD Driver Circuit................................................................................................................................20 LCD Drive Power Supply Circuit..........................................................................................................20 Internal logic power supply regulator ....................................................................................................20 GRAM Address MAP ................................................................................................................................21 Instructions .................................................................................................................................................29 Outline ...................................................................................................................................................29 Instruction Data Format.........................................................................................................................29 Instruction Description ..........................................................................................................................31 Index (IR) ..............................................................................................................................................31 Device code read (R00h) .......................................................................................................................31 Driver output control (R01h) .................................................................................................................31 LCD Driving Wave Control (R02h) ......................................................................................................31 Entry Mode (R03h)................................................................................................................................32 Resizing Control (R04h)........................................................................................................................35 Display Control 1 (R07h) ......................................................................................................................36 Display Control 2 (R08h) ......................................................................................................................37 Display Control 3 (R09h) ......................................................................................................................38 Display Control 4 (R0Ah) .....................................................................................................................39 External Display Interface Control 1 (R0Ch) ........................................................................................40 Frame Maker Position (R0Dh) ..............................................................................................................42 External Display Interface Control 2 (R0Fh).........................................................................................42 Power Control 1 (R10h).........................................................................................................................43 Power Control 2 (R11h).........................................................................................................................45 Power Control 3 (R12h).........................................................................................................................46 Power Control 4 (R13h).........................................................................................................................47 Regulator Control (R15h) .....................................................................................................................48 IPS Control (R16h)...............................................................................................................................49 RAM Address Set (Horizontal Address) (R20h) ...................................................................................50
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LGDP4531
Rev 1.15
RAM Address Set (Vertical Address) (R21h) .......................................................................................50 Write Data to RAM (R22h) ..................................................................................................................51 Read Data from RAM (R22h) ...............................................................................................................54 Gamma Control 1-10 (R30h to R39h) ...................................................................................................55 EPROM Control Register 1 (R40h).......................................................................................................56 EPROM Control Register 2 (R41h).......................................................................................................56 EPROM Control Register 3 (R42h).......................................................................................................56 Window Horizontal RAM Address Start/End (R50h/R51h) .................................................................57 Window Vertical RAM Address Start/End (R52h/R53h)......................................................................57 Driver Output Control (R60h) ...............................................................................................................58 Base Image Display Control (R61h)......................................................................................................58 www..com Vertical Scroll Control (R6Ah)..............................................................................................................58 Partial Image 1: Display Position (R80h) ..............................................................................................61 RAM Address (Start/End Line Address) (R81h/R82h) .........................................................................61 Partial Image 2: Display Position (R83h) ..............................................................................................61 RAM Address (Start/End Line Address) (R84h/R85h) .........................................................................61 Panel Interface Control 1 (R90h)...........................................................................................................62 Panel Interface Control 2 (R92h)...........................................................................................................63 Panel Interface Control 3 (R93h)...........................................................................................................64 Panel Interface Control 4 (R95h)...........................................................................................................64 Panel Interface Control 5 (R97h)...........................................................................................................66 Panel Interface Control 6 (R98h)...........................................................................................................67 Test Register 1 (RA0h)..........................................................................................................................67 Test Register 2 (RA1h)..........................................................................................................................68 Test Register 3 (RA2h)..........................................................................................................................68 Instruction List ...........................................................................................................................................69 Reset Function............................................................................................................................................71 Basic Mode operation of the LGDP4531 ...................................................................................................73 Interface and data format............................................................................................................................74 System Interface .........................................................................................................................................77 80-system 18-bit Bus Interface ..............................................................................................................78 80-system 16-bit Bus Interface ..............................................................................................................79 Data Transfer Synchronous in 16-bit Bus Interface operation...............................................................80 80-system 9-bit Bus Interface ................................................................................................................81 Data Transfer Synchronous in 9-bit Bus Interface operation.................................................................82 80-system 8-bit Bus Interface ................................................................................................................83 Data Transfer Synchronous in 8-bit Bus Interface operation.................................................................85 Serial Interface.......................................................................................................................................86 VSYNC Interface .......................................................................................................................................89 Notes in using the VSYNC interface.....................................................................................................91 External Display Interface..........................................................................................................................93 RGB Interface........................................................................................................................................93 Polarities of VSYNC, HSYNC, ENABLE, and DOTCLK Signals.......................................................94 RGB Interface Timing ...........................................................................................................................94 Moving Picture Display with the RGB Interface...................................................................................95 RAM access via system interface in RGB interface operation ..............................................................96 6-bit RGB Interface ...............................................................................................................................97 Data Transfer Synchronization in 6-bit Bus Interface operation ...........................................................98 16-bit RGB Interface .............................................................................................................................99 18-bit RGB Interface ...........................................................................................................................100 Notes on Using the External Display Interface....................................................................................101 RAM Address and Display Position on the Panel ....................................................................................103 Restrictions in setting display control instruction................................................................................104 Screen setting.......................................................................................................................................104 Instruction setting example..................................................................................................................105 Resizing function......................................................................................................................................108 Resizing setting....................................................................................................................................108
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LGDP4531
Rev 1.15
Notes to Resizing function...................................................................................................................109 FMARK function .....................................................................................................................................111 FMP setting example ...........................................................................................................................112 Display operation synchronous data transfer using FMARK ..............................................................112 Window Address Function .......................................................................................................................114 EPROM Control .......................................................................................................................................115 Scan Mode Setting....................................................................................................................................117 8-color Display Mode...............................................................................................................................118 Line Inversion AC Drive ..........................................................................................................................119 Frame-Frequency Adjustment Function...................................................................................................120 Relationship between the liquid crystal Drive Duty and the Frame Frequency...................................120 www..comPartial Display Function ...........................................................................................................................121 Liquid crystal panel interface timing........................................................................................................122 Internal clock operation .......................................................................................................................122 RGB Interface operation......................................................................................................................123 Oscillator ..................................................................................................................................................124 -Correction Function...............................................................................................................................125 Grayscale Amplifier Unit Configuration .............................................................................................126 -Correction Register...........................................................................................................................129 Ladder Resistors and 8-to-1 Selector...................................................................................................130 Power-supply Generating Circuit .............................................................................................................136 Power supply circuit connection example 1 (Vci1 = VciOUT)...........................................................136 Power supply circuit connection example2 (Vci1 = Vci direct input).................................................137 Specifications of Power-supply Circuit External Elements......................................................................138 Voltage Setting Pattern Diagram..............................................................................................................139 Power Supply Instruction Setting .............................................................................................................140 Instruction Setting ....................................................................................................................................141 Display ON/OFF sequence ..................................................................................................................141 Sleep mode SET/EXIT sequences .......................................................................................................142 Deep standby mode IN/EXIT sequences ............................................................................................143 8-color mode setting ............................................................................................................................143 Parital Display setting..........................................................................................................................144 Absolute Maximum Ratings.....................................................................................................................145 Electrical Characteristics ..........................................................................................................................146 DC Characteristics ...............................................................................................................................146 80-System Bus Interface Timing Characteristics (18/16-Bit Bus).......................................................146 80-System Bus Interface Timing Characteristics (8/9-Bit Bus) ..........................................................147 Serial Peripheral Interface Timing Characteristics .............................................................................147 RGB Interface Timing Characteristics.................................................................................................148 Reset Timing Characteristics ...............................................................................................................148 LCD Driver Output Characteristics .....................................................................................................148 Notes to Electrical Characteristics.......................................................................................................149 Timing characteristic diagram .............................................................................................................150
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LGDP4531
Rev 1.15
Description
The LGDP4531 is a one-chip liquid crystal controller driver LSI, comprising RAM of 240 RGB x 320 dots at maximum, a source driver, a gate driver and a power supply circuit. For effective data transfer, the LGDP4531 supports high-speed 8-/9-/16-/18-bit bus interfaces as a system interface to microcomputer and high-speed RAM write mode. As a moving picture interface, the LGDP4531 supports RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, DB17-0). Also, the LGDP4531 incorporates step-up circuits and voltage follower circuits to generate TFT liquid crystal panel drive voltages. www..comThe LGDP4531's power management functions such as 8-color display and deep standby and so on make this LSI an ideal driver for the medium or small sized portable products with color display systems such as digital cellular phones or small PDAs, where long battery life is a major concern.
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LGDP4531
Rev 1.15
Features
A one-chip controller driver incorporating a gate circuit and a power supply circuit for 240RGB x320 dots graphics display on an amorphous TFT panel in 262k colors System interface - High-speed interfaces via 8-, 9-, 16-, 18-bit parallel ports - Serial interface Interface for moving picture display - 6-, 16-, 18-bit bus RGB interfaces (VSYNC, HSYNC, DOTCLK, ENABLE, DB17-0) - VSYNC interface (System interface + VSYNC) - FMARK interface (System interface + FMARK) Window address function to specify a rectangular area on the internal RAM to write data Writes data within a rectangular area on the internal RAM via moving picture interface - Reduces data transfer by specifying the area on the RAM to rewrite data - Enables displaying the data in the still picture RAM area with a moving picture simultaneously - Resizing function (x 1/2, x 1/4) Abundant color display and drawing functions - Programmable -correction function for 262k-color display - Partial display function Low -power consumption architecture (allowing direct input of interface I/O power supply) - Deep standby function - 8-color display function - Input power supply voltages: Vcc = 2.5V ~ 3.3 V (logic regulator power supply) IOVcc = 1.65V ~ 3.3 V (interface I/O power supply) Vci = 2.5V ~ 3.3 V (liquid crystal analog circuit power supply) Incorporates a liquid crystal drive power supply circuit - Source driver liquid crystal drive/Vcom power supply: DDVDH-GND = 4.5V ~ 6.0 V - Gate drive power supply: VGH-GND = 10.0V ~ 15.0 V VGL-GND = -4.5V ~ -12.5V VGH-VGL 25V Liquid crystal power supply startup sequence TFT storage capacitance: Cst only (common Vcom formula) 172,800-byte internal RAM Internal 720-channel source driver and 320-channel gate driver Configures a COG module with one chip by arranging gate lines on both sides
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LGDP4531
Rev 1.15
Block Diagram
RGND
Index Register (IR)
GND
Control Register (CR)
Address counter
AGND IOGND
IM3-1, IM0/ID
18
BGR circuit
Write data latch
18
Graphic RAM (GRAM)
S1-S720
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CS* RS WR/SCL RD* SDI SDO DB017-0
System Interface 18-bit 16-bit 9-bit 8-bit 8-bit serial Read data latch 172,800 bytes
18
18
V63-V0
External display Interface
VSYNC HSYNC DOTCLK ENABLE
Timing genrator
DB17-0 VSYNC HSYNC DOTCLK ENABLE
FMARK RESET* OSC2 OSC1 G1-G320
CPG
Internal reference voltage generating circuit
VCC
Internal logic power supply regulator
VPP1-3 TEST1
VDD
Liquid crystal drive level generating circuit
Figure 1
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LGDP4531
Rev 1.15
Pin Function
Table 1 Signal IM3-1, IM0/ID
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I/O I
Connected to GND/ IOVcc
Function Select a mode to interface to an MPU. In SPI mode, the IM0 pin is used to set the ID of device code.
IM[3:0] 000* 0010 0011 010* 011* 100* 1010 1011 11** Interface Mode Setting disabled 80-system 16-bit interface 80-system 8-bit interface Serial peripheral interface (SPI) Setting disabled Setting disabled 80-system 18-bit interface 80-system 9-bit interface Setting disabled DB Pins DB[17:10], DB[8:1] DB[17:10] SDI, SDO DB[17:0] DB[17:9] -
CS*
I
MPU
RS
I
MPU
WR*/SCL
I
MPU
RD*
I
MPU
SDI
I
MPU
SDO
O
MPU
DB0 ~ DB17 ENABLE
I/O I
MPU MPU
VSYNC
I
MPU
A chip select signal. Amplitude: IOVCC-GND. Low: LGDP4531 is selected and accessible. High: LGDP4531 is not selected and not accessible. Fix to the GND level when not in use. A register select signal. Amplitude: IOVCC-GND. Low: select the index/status register. High: select a control register. In SPI mode, fix to either IOVcc or GND level. Outputs a write strobe signal in 80-system bus interface mode and enables an operation to write data when the signal is low. In SPI mode, a synchronizing clock signal is output. Outputs a read strobe signal in 80-system bus interface mode and enables an operation to read data when the signal is low. In SPI mode, fix to either IOVcc or GND level. A serial data input (SDI) pin in SPI mode. Data are input on the rising edge of the SCL signal. Fix to either IOVcc or GND level when not in use. A serial data output (SDO) pin in SPI mode. Data are output on the falling edge of the SCL signal. Leave the pin open when not in use. An 18-bit parallel bidirectional data bus. Unused pins must be fixed either IOVcc or GND level. A data enable signal in RGB interface mode. Low: Select (accessible) High: Not select (inaccessible) The EPL bit inverts the polarity of the ENABLE signal. Fix to either IOVcc or GND level when not in use. A frame synchronizing signal. When VSPL = "0", it is active low. When VSPL = "1", it is active high. Fix to either IOVcc or GND level when not in use.
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LGDP4531
Rev 1.15
HSYNC
I
MPU
DOTCLK
I
MPU
RESET*
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I
VCMSEL
I
MPU or External RC circuit IOVcc or GND
FMARK OSC1 OSC2 Vcc GND RGND
O I/O I -
MPU Oscillation Resistor Power supply Power supply Power supply Stabilizing capacitor Power supply
A line synchronizing signal. When HSPL = "0", it is active low. When HSPL = "1", it is active high. Fix to either IOVcc or GND level when not in use. A dot clock signal. When DPL = "0", input data on the rising edge of DOTCLK. When DPL = "1", input data on the falling edge of DOTCLK. Fix to either IOVcc or GND level when not in use. A reset pin. Initializes the LGDP4531 with a low input. Be sure to execute a power-on reset after supplying power. If VCMSEL is set to high, VCOMH level control comes from EPROM block. If VCMSEL is set to low, VCOMH level control comes from internal registers set by MPU. Connect to GND when EPROM is not used. Frame head pulse signal, which is used when writing data to the internal GRAM. Leave the pin open when not in use. Connect to an external resistor for R-C oscillation. Power supply to internal logic regulator circuit: Vcc =2.5V ~ 3.3 V Vcc IOVcc Internal logic GND : GND = 0V Internal RAM GND : RGND must be at the same electrical potential as GND. In case of COG, connect to GND on the FPC to prevent noise. Internal logic regulator output to be used as a power supply to internal logic. Connect a stabilizing capacitor. Power supply to the interface pins: RESET*, CS*, WR, RD*, RS, DB17-0, VSYNC, HSYNC, DOTCLK, ENABLE. IOVcc = 1.65V ~ 3.3V. Vcc IOVcc. . In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent nosie. GND for the interface pins : RESET*, CS*, WR, RD*, RS, DB17-0, VSYNC, HSYNC, DOTCLK, ENABLE. IOGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. Analog GND (for logic regulator and liquid crystal power supply circuit): AGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. Power supply to liquid crystal power supply analog circuit. Connect to an external power supply of 2.5V ~ 3.3V. Internal reference voltage generated between Vci and GND. The output level is set by instruction (VC). Reference voltage for the step-up circuit 1. Vci1 must be set to a level, which will generate the VLOUT1, VLOUT2 and VLOUT3 levels within the respective setting ranges. Reference level to generate the VciOUT level according to the step-up rate set with the VC bits. Be sure to connect VciLVL with Vci on the FPC to prevent noise.
VDD IOVcc
O I
IOGND
-
Power supply
AGND
-
Power supply Power supply Stabilizing capactor, Vci1 VciOUT or Vci Power supply
Vci VciOUT
I O
Vci1
I/O
VciLVL
I
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LGDP4531
Rev 1.15
VLOUT1
O
DDVDH VLOUT2
I O
Stabilizing capacitor, DDVDH VLOUT1 Stabilizing capacitor, VGH VLOUT2 Stabilizing capacitor, VGL VLOUT3 Stabilizing capacitor, VCL VLOUT4 Step-up capacitor Step-up capacitor
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VGH VLOUT3
I O
VGL VLOUT4
I O
VCL C11+, C11C12+, C12C13+, C13C21+, C21C22+, C22C23+, C23VREG1OUT
I I/O I/O
Output from the step-up circuit 1, generated from Vci1. The step-up factor for the VLOUT1 level is set by instruction (BT). VLOUT1 = 4.5V ~ 6.0V Power supply for the source driver liquid crystal drive unit and Vcom drive. Connect to VLOUT1. DDVDH = 4.5V ~ 6.0V Output from the step-up circuit 2, generated from Vci1 and DDVDH. The step-up factor for VLOUT2 is set by instruction (BT). VLOUT2 = max 15.0V Liquid crystal drive power supply. Connect to VLOUT2. Output from the step-up circuit 2, generated from Vci1 and DDVDH. The step-up factor for VLOUT2 is set by instruction (BT). VLOUT3 = min -12.5V Liquid crystal drive power supply. Connect to VLOUT3. A voltage level of Vci1 x (-1) generated in the step=ip circuit 2. Connect to a stabilizing capacitor when using the VLOUT4 output. Power supply for operating VCOML. Vci1 is multiplied by 1 and output by internal step-up circuit 2. VCL = 0 to -3.3(V) Pins to connect capacitors for the step-up circuit 1. Pins to connect capacitors for the step-up circuit 2. Connect capacitors where they are required according to the step-up factor. Output generated from a reference voltage VciLVL by amplifying by the factor, which is set by instruction (VRH). VREG1OUT is used for (1) source driver grayscale reference voltage, (2) VCOMH level reference voltage, and (3) Vcom amplitude reference voltage. Connect to a stabilizing capacitor when it is in use. VREG1OUT = 3.0V ~ (DDVDH - 0.5)V Power supply to TFT panel's common electrode. Output AC voltage with the amplitude VCOMH and VCOML. The alternating cycle is changeable by register setting. Also Vcom output can be started and halted by register setting. Output for the high level of VCOM. This output voltage is adjusted by an instruction (VCM) setting. VCOMH = 3.0 to (DDVDH -0.5) (V) Output for the low level of VCOM. This output voltage is adjusted by an instruction (VDV) setting or fixed to GND by a register (VCOMG) setting. In this case, a capacitor for stabilization is not necessary. VCOML = (VCL +0.5)to 1 (V) If a variable resistor is used to adjust VCOMH, it is attached to this pin. In this case, use an instruction (VCM) setting to stop the internal digital potentiometer circuit of VCOMH, and insert the variable resistor for use in adjustment of VCOM between VREG1OUT. Leave it open or connect to GND when not in use. Reference level for grayscale voltage generating circuit.
O
Stabilizing capacitor
Vcom
O
TFT panel common electrode Stabilizing capacitor Stabilizing capacitor
VCOMH
O
VCOML
O
VcomR
I
Variable resistor or open
VGS
I
GND
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LGDP4531
Rev 1.15
S1 ~ S720
O
LCD
G1 ~ G320
O
LCD
V0T,V31T
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VREFC VREF VDDTEST VREFD VMON IOVCCDUM 1-2 VCCDUM1 IOGNDDUM 1-3 OSC1DUM 1-4 OSC2DUM 1-2 AGNDDUM 1-4 DUMMYR 1-2 DUMMYR 3-4 DUMMYR 5-10 TEST1 TEST2 - 5 TESTA5 TSC TS8-0 VPP1, VPP3 VPP2 TESTO1-38
I I -
GND Power supply -
Liquid crystal application voltage. To change the shift direction of segment signal outputs, set the SS bit as follows. When SS = 0, the data in the RAM address h00000 is output from S1. When SS = 1, the data in the RAM address h00000 is output from S720. Gate line output signals. VGH: gate line select level VGL: gate line non-select level Test pins. Connect to IOVCC, GND or open when not in use. Test pin. Connect to IOVCC, GND or open when not in use. Test pin. Connect to IOVCC, GND or open when not in use. Test pin. Connect to IOVCC, GND or open when not in use. Test pin. Connect to IOVCC, GND or open when not in use. Test pin. Connect to IOVCC, GND or open when not in use. Test pin. Connect to IOVCC, GND or open when not in use. Use them to fix the electrical potentials of unused interface pins and fixed pins. When not in use, leave them open. Use them to fix the electrical potentials of unused interface pins and fixed pins. When not in use, leave it open. Use them to fix the electrical potentials of unused interface pins and fixed pins. When not in use, leave it open. Test pins. Connect to IOVCC, GND or open when not in use. Test pins. Connect to IOVCC, GND or open when not in use. Use them to fix the electrical potentials of unused interface pins and fixed pins. When not in use, leave it open. Dummy pins. Connect to IOVCC, GND or open when not in use. DUMMYR3 and DUMMYR4 are short-circuited within the chip for COG contact resistance measurement. Dummy pins. Connect to IOVCC, GND or open when not in use. Test pin. Connect to GND. Test pins. Connect to IOVCC, GND or open when not in use. Test pin. Connect to IOVCC, GND or open when not in use. Test pin. Connect to IOVCC, GND or open when not in use. Test pins. Connect to IOVCC, GND or open when not in use. Test pins. Connect to IOVCC, GND or open when not in use. Power supply pin for EPROM write operation. Leave it open when EPROM is not used. Test pins. Connect to IOVCC, GND or open when not in use.
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LGDP4531
Rev 1.15
PAD Arrangement
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LGDP4531
Rev 1.15
PAD Coordinate
Pad # . 1 2 3 4 5 6 7 8 9 10 11 12 13 www..com 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PAD Name DUMMYR1 DUMMYR2 TESTO1 VCCDUM1 VPP1 VPP1 VPP1 VPP2 VPP2 VPP2 VPP2 VPP2 VPP3 VCMSEL VCMSEL TESTO2 IOGNDDUM1 TESTO3 TEST1 TEST2 TEST4 TEST5 TEST3 IM0/ID IM1 IM2 IM3 TESTO4 IOVCCDUM1 TESTO5 RESET* VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 TESTO6 IOGNDDUM2 TESTO7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDO SDI RD* WR*/SCL RS CS* TESTO8 IOVCCDUM2 TESTO9 FMARK TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 TSC TESTO10 IOGNDDUM3 TESTO11 TESTO12 OSC1DUM1 OSC1DUM2 OSC1 OSC1DUM3 X -10395.0 -10325.0 -10255.0 -10185.0 -10115.0 -10045.0 -9975.0 -9905.0 -9835.0 -9765.0 -9695.0 -9625.0 -9555.0 -9485.0 -9415.0 -9345.0 -9275.0 -9205.0 -9135.0 -9065.0 -8995.0 -8925.0 -8855.0 -8785.0 -8715.0 -8645.0 -8575.0 -8505.0 -8435.0 -8365.0 -8295.0 -8225.0 -8155.0 -8085.0 -8015.0 -7945.0 -7875.0 -7805.0 -7735.0 -7665.0 -7595.0 -7525.0 -7455.0 -7385.0 -7315.0 -7245.0 -7175.0 -7105.0 -7035.0 -6965.0 -6895.0 -6825.0 -6755.0 -6685.0 -6615.0 -6545.0 -6475.0 -6405.0 -6335.0 -6265.0 -6195.0 -6125.0 -6055.0 -5985.0 -5915.0 -5845.0 -5775.0 -5705.0 -5635.0 -5565.0 -5495.0 -5425.0 -5355.0 -5285.0 -5215.0 -5145.0 -5075.0 -5005.0 -4935.0 -4865.0 -4795.0 -4725.0 -4655.0 -4585.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 Pad # . 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PAD Name OSC1DUM4 OSC2 OSC2DUM1 OSC2DUM2 DUMMYR3 DUMMYR4 IOGND IOGND IOGND IOGND IOGND IOGND IOGND IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCC VCC VDDOUT VDDOUT VDDOUT VDDOUT VDD VDD VDD VDD VDD VDD VDD VDD VDD TESTO13 VREFD TESTO14 VREF TESTO15 VREFC TESTO16 VDDTEST AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND GND GND GND GND GND GND RGND RGND RGND RGND RGND RGND RGND RGND RGND RGND TESTO17 VTEST TESTO18 VGS TESTO19 V0T TESTO20 VMON X -4515.0 -4445.0 -4375.0 -4305.0 -4235.0 -4165.0 -4095.0 -4025.0 -3955.0 -3885.0 -3815.0 -3745.0 -3675.0 -3605.0 -3535.0 -3465.0 -3395.0 -3325.0 -3255.0 -3185.0 -3115.0 -3045.0 -2975.0 -2905.0 -2835.0 -2765.0 -2695.0 -2625.0 -2555.0 -2485.0 -2415.0 -2345.0 -2275.0 -2205.0 -2135.0 -2065.0 -1995.0 -1925.0 -1855.0 -1785.0 -1715.0 -1645.0 -1575.0 -1505.0 -1435.0 -1365.0 -1295.0 -1225.0 -1155.0 -1085.0 -1015.0 -945.0 -875.0 -805.0 -735.0 -665.0 -595.0 -525.0 -455.0 -385.0 -315.0 -245.0 -175.0 -105.0 -35.0 35.0 105.0 175.0 245.0 315.0 385.0 455.0 525.0 595.0 665.0 735.0 805.0 875.0 945.0 1015.0 1085.0 1155.0 1225.0 1295.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 Pad # . 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 PAD Name TESTO21 V31T VCOM1 VCOM1 VCOM1 VCOM2 VCOM2 VCOM2 VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML TESTO22 TESTO23 VREG1OUT TESTO24 TESTA5 TESTO25 VCOMR TESTO26 VLOUT4 VCL VCL VLOUT1 VLOUT1 VLOUT1 VLOUT1 VLOUT1 DDVDH DDVDH DDVDH DDVDH DDVDH VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCI1 VCILVL VCI VCI VCI VCI VCI VCI VCI VCI C12C12C12C12C12C12+ C12+ C12+ C12+ C12+ C11C11C11C11C11C11+ C11+ C11+ C11+ C11+ AGNDDUM1 VLOUT3 VLOUT3 VLOUT3 VLOUT3 VGL X 1365.0 1435.0 1505.0 1575.0 1645.0 1715.0 1785.0 1855.0 1925.0 1995.0 2065.0 2135.0 2205.0 2275.0 2345.0 2415.0 2485.0 2555.0 2625.0 2695.0 2765.0 2835.0 2905.0 2975.0 3045.0 3115.0 3185.0 3255.0 3325.0 3395.0 3465.0 3535.0 3605.0 3675.0 3745.0 3815.0 3885.0 3955.0 4025.0 4095.0 4165.0 4235.0 4305.0 4375.0 4445.0 4515.0 4585.0 4655.0 4725.0 4795.0 4865.0 4935.0 5005.0 5075.0 5145.0 5215.0 5285.0 5355.0 5425.0 5495.0 5565.0 5635.0 5705.0 5775.0 5845.0 5915.0 5985.0 6055.0 6125.0 6195.0 6265.0 6335.0 6405.0 6475.0 6545.0 6615.0 6685.0 6755.0 6825.0 6895.0 6965.0 7035.0 7105.0 7175.0 Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5
12
LGDP4531
Rev 1.15
Pad # . 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 www..com 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339
PAD Name VGL VGL VGL VGL VGL VGL VGL AGNDDUM2 AGNDDUM3 AGNDDUM4 VLOUT2 VLOUT2 VGH VGH VGH VGH TESTO27 C13C13C13TESTO28 C13+ C13+ C13+ TESTO29 C21C21C21C21+ C21+ C21+ C22C22C22C22+ C22+ C22+ C23C23C23C23+ C23+ C23+ TESTO30 DUMMYR5 DUMMYR6 TESTO31 TESTO32 DUMMYR7 DUMMYR8 VGLDMY1 G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 G59 G61 G63 G65 G67 G69 G71
X 7245.0 7315.0 7385.0 7455.0 7525.0 7595.0 7665.0 7735.0 7805.0 7875.0 7945.0 8015.0 8085.0 8155.0 8225.0 8295.0 8365.0 8435.0 8505.0 8575.0 8645.0 8715.0 8785.0 8855.0 8925.0 8995.0 9065.0 9135.0 9205.0 9275.0 9345.0 9415.0 9485.0 9555.0 9625.0 9695.0 9765.0 9835.0 9905.0 9975.0 10045.0 10115.0 10185.0 10255.0 10325.0 10395.0 10670.0 10650.0 10630.0 10610.0 10590.0 10570.0 10550.0 10530.0 10510.0 10490.0 10470.0 10450.0 10430.0 10410.0 10390.0 10370.0 10350.0 10330.0 10310.0 10290.0 10270.0 10250.0 10230.0 10210.0 10190.0 10170.0 10150.0 10130.0 10110.0 10090.0 10070.0 10050.0 10030.0 10010.0 9990.0 9970.0 9950.0 9930.0 9910.0 9890.0 9870.0
Y -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 -517.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
Pad # . 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426
PAD Name G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 G95 G97 G99 G101 G103 G105 G107 G109 G111 G113 G115 G117 G119 G121 G123 G125 G127 G129 G131 G133 G135 G137 G139 G141 G143 G145 G147 G149 G151 G153 G155 G157 G159 G161 G163 G165 G167 G169 G171 G173 G175 G177 G179 G181 G183 G185 G187 G189 G191 G193 G195 G197 G199 G201 G203 G205 G207 G209 G211 G213 G215 G217 G219 G221 G223 G225 G227 G229 G231 G233 G235 G237 G239 G241 G243 G245
X 9850.0 9830.0 9810.0 9790.0 9770.0 9750.0 9730.0 9710.0 9690.0 9670.0 9650.0 9630.0 9610.0 9590.0 9570.0 9550.0 9530.0 9510.0 9490.0 9470.0 9450.0 9430.0 9410.0 9390.0 9370.0 9350.0 9330.0 9310.0 9290.0 9270.0 9250.0 9230.0 9210.0 9190.0 9170.0 9150.0 9130.0 9110.0 9090.0 9070.0 9050.0 9030.0 9010.0 8990.0 8970.0 8950.0 8930.0 8910.0 8890.0 8870.0 8850.0 8830.0 8810.0 8790.0 8770.0 8750.0 8730.0 8710.0 8690.0 8670.0 8650.0 8630.0 8610.0 8590.0 8570.0 8550.0 8530.0 8510.0 8490.0 8470.0 8450.0 8430.0 8410.0 8390.0 8370.0 8350.0 8330.0 8310.0 8290.0 8270.0 8250.0 8230.0 8210.0 8190.0 8170.0 8150.0 8130.0
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5
Pad # . 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513
PAD Name G247 G249 G251 G253 G255 G257 G259 G261 G263 G265 G267 G269 G271 G273 G275 G277 G279 G281 G283 G285 G287 G289 G291 G293 G295 G297 G299 G301 G303 G305 G307 G309 G311 G313 G315 G317 G319 VGLDMY2 TESTO33 TESTO34 S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 S709 S708 S707 S706 S705 S704 S703 S702 S701 S700 S699 S698 S697 S696 S695 S694 S693 S692 S691 S690 S689 S688 S687 S686 S685 S684 S683 S682 S681 S680 S679 S678 S677 S676 S675 S674
X 8110.0 8090.0 8070.0 8050.0 8030.0 8010.0 7990.0 7970.0 7950.0 7930.0 7910.0 7890.0 7870.0 7850.0 7830.0 7810.0 7790.0 7770.0 7750.0 7730.0 7710.0 7690.0 7670.0 7650.0 7630.0 7610.0 7590.0 7570.0 7550.0 7530.0 7510.0 7490.0 7470.0 7450.0 7430.0 7410.0 7390.0 7370.0 7350.0 7130.0 7110.0 7090.0 7070.0 7050.0 7030.0 7010.0 6990.0 6970.0 6950.0 6930.0 6910.0 6890.0 6870.0 6850.0 6830.0 6810.0 6790.0 6770.0 6750.0 6730.0 6710.0 6690.0 6670.0 6650.0 6630.0 6610.0 6590.0 6570.0 6550.0 6530.0 6510.0 6490.0 6470.0 6450.0 6430.0 6410.0 6390.0 6370.0 6350.0 6330.0 6310.0 6290.0 6270.0 6250.0 6230.0 6210.0 6190.0
Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5
13
LGDP4531
Rev 1.15
Pad # . 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 www..com 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
PAD Name S673 S672 S671 S670 S669 S668 S667 S666 S665 S664 S663 S662 S661 S660 S659 S658 S657 S656 S655 S654 S653 S652 S651 S650 S649 S648 S647 S646 S645 S644 S643 S642 S641 S640 S639 S638 S637 S636 S635 S634 S633 S632 S631 S630 S629 S628 S627 S626 S625 S624 S623 S622 S621 S620 S619 S618 S617 S616 S615 S614 S613 S612 S611 S610 S609 S608 S607 S606 S605 S604 S603 S602 S601 S600 S599 S598 S597 S596 S595 S594 S593 S592 S591 S590 S589 S588 S587
X 6170.0 6150.0 6130.0 6110.0 6090.0 6070.0 6050.0 6030.0 6010.0 5990.0 5970.0 5950.0 5930.0 5910.0 5890.0 5870.0 5850.0 5830.0 5810.0 5790.0 5770.0 5750.0 5730.0 5710.0 5690.0 5670.0 5650.0 5630.0 5610.0 5590.0 5570.0 5550.0 5530.0 5510.0 5490.0 5470.0 5450.0 5430.0 5410.0 5390.0 5370.0 5350.0 5330.0 5310.0 5290.0 5270.0 5250.0 5230.0 5210.0 5190.0 5170.0 5150.0 5130.0 5110.0 5090.0 5070.0 5050.0 5030.0 5010.0 4990.0 4970.0 4950.0 4930.0 4910.0 4890.0 4870.0 4850.0 4830.0 4810.0 4790.0 4770.0 4750.0 4730.0 4710.0 4690.0 4670.0 4650.0 4630.0 4610.0 4590.0 4570.0 4550.0 4530.0 4510.0 4490.0 4470.0 4450.0
Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
Pad # . 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687
PAD Name S586 S585 S584 S583 S582 S581 S580 S579 S578 S577 S576 S575 S574 S573 S572 S571 S570 S569 S568 S567 S566 S565 S564 S563 S562 S561 S560 S559 S558 S557 S556 S555 S554 S553 S552 S551 S550 S549 S548 S547 S546 S545 S544 S543 S542 S541 S540 S539 S538 S537 S536 S535 S534 S533 S532 S531 S530 S529 S528 S527 S526 S525 S524 S523 S522 S521 S520 S519 S518 S517 S516 S515 S514 S513 S512 S511 S510 S509 S508 S507 S506 S505 S504 S503 S502 S501 S500
X 4430.0 4410.0 4390.0 4370.0 4350.0 4330.0 4310.0 4290.0 4270.0 4250.0 4230.0 4210.0 4190.0 4170.0 4150.0 4130.0 4110.0 4090.0 4070.0 4050.0 4030.0 4010.0 3990.0 3970.0 3950.0 3930.0 3910.0 3890.0 3870.0 3850.0 3830.0 3810.0 3790.0 3770.0 3750.0 3730.0 3710.0 3690.0 3670.0 3650.0 3630.0 3610.0 3590.0 3570.0 3550.0 3530.0 3510.0 3490.0 3470.0 3450.0 3430.0 3410.0 3390.0 3370.0 3350.0 3330.0 3310.0 3290.0 3270.0 3250.0 3230.0 3210.0 3190.0 3170.0 3150.0 3130.0 3110.0 3090.0 3070.0 3050.0 3030.0 3010.0 2990.0 2970.0 2950.0 2930.0 2910.0 2890.0 2870.0 2850.0 2830.0 2810.0 2790.0 2770.0 2750.0 2730.0 2710.0
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5
Pad # . 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774
PAD Name S499 S498 S497 S496 S495 S494 S493 S492 S491 S490 S489 S488 S487 S486 S485 S484 S483 S482 S481 S480 S479 S478 S477 S476 S475 S474 S473 S472 S471 S470 S469 S468 S467 S466 S465 S464 S463 S462 S461 S460 S459 S458 S457 S456 S455 S454 S453 S452 S451 S450 S449 S448 S447 S446 S445 S444 S443 S442 S441 S440 S439 S438 S437 S436 S435 S434 S433 S432 S431 S430 S429 S428 S427 S426 S425 S424 S423 S422 S421 S420 S419 S418 S417 S416 S415 S414 S413
X 2690.0 2670.0 2650.0 2630.0 2610.0 2590.0 2570.0 2550.0 2530.0 2510.0 2490.0 2470.0 2450.0 2430.0 2410.0 2390.0 2370.0 2350.0 2330.0 2310.0 2290.0 2270.0 2250.0 2230.0 2210.0 2190.0 2170.0 2150.0 2130.0 2110.0 2090.0 2070.0 2050.0 2030.0 2010.0 1990.0 1970.0 1950.0 1930.0 1910.0 1890.0 1870.0 1850.0 1830.0 1810.0 1790.0 1770.0 1750.0 1730.0 1710.0 1690.0 1670.0 1650.0 1630.0 1610.0 1590.0 1570.0 1550.0 1530.0 1510.0 1490.0 1470.0 1450.0 1430.0 1410.0 1390.0 1370.0 1350.0 1330.0 1310.0 1290.0 1270.0 1250.0 1230.0 1210.0 1190.0 1170.0 1150.0 1130.0 1110.0 1090.0 1070.0 1050.0 1030.0 1010.0 990.0 970.0
Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
14
LGDP4531
Rev 1.15
Pad # . 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 www..com 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861
PAD Name S412 S411 S410 S409 S408 S407 S406 S405 S404 S403 S402 S401 S400 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326
X 950.0 930.0 910.0 890.0 870.0 850.0 830.0 810.0 790.0 770.0 750.0 730.0 710.0 690.0 670.0 650.0 630.0 610.0 590.0 570.0 550.0 530.0 510.0 490.0 470.0 450.0 430.0 410.0 390.0 370.0 350.0 330.0 310.0 290.0 270.0 250.0 230.0 210.0 190.0 170.0 150.0 130.0 110.0 90.0 70.0 50.0 30.0 10.0 -10.0 -30.0 -50.0 -70.0 -90.0 -110.0 -130.0 -150.0 -170.0 -190.0 -210.0 -230.0 -250.0 -270.0 -290.0 -310.0 -330.0 -350.0 -370.0 -390.0 -410.0 -430.0 -450.0 -470.0 -490.0 -510.0 -530.0 -550.0 -570.0 -590.0 -610.0 -630.0 -650.0 -670.0 -690.0 -710.0 -730.0 -750.0 -770.0
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5
Pad # . 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948
PAD Name S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239
X -790.0 -810.0 -830.0 -850.0 -870.0 -890.0 -910.0 -930.0 -950.0 -970.0 -990.0 -1010.0 -1030.0 -1050.0 -1070.0 -1090.0 -1110.0 -1130.0 -1150.0 -1170.0 -1190.0 -1210.0 -1230.0 -1250.0 -1270.0 -1290.0 -1310.0 -1330.0 -1350.0 -1370.0 -1390.0 -1410.0 -1430.0 -1450.0 -1470.0 -1490.0 -1510.0 -1530.0 -1550.0 -1570.0 -1590.0 -1610.0 -1630.0 -1650.0 -1670.0 -1690.0 -1710.0 -1730.0 -1750.0 -1770.0 -1790.0 -1810.0 -1830.0 -1850.0 -1870.0 -1890.0 -1910.0 -1930.0 -1950.0 -1970.0 -1990.0 -2010.0 -2030.0 -2050.0 -2070.0 -2090.0 -2110.0 -2130.0 -2150.0 -2170.0 -2190.0 -2210.0 -2230.0 -2250.0 -2270.0 -2290.0 -2310.0 -2330.0 -2350.0 -2370.0 -2390.0 -2410.0 -2430.0 -2450.0 -2470.0 -2490.0 -2510.0
Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
Pad # . 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035
PAD Name S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152
X -2530.0 -2550.0 -2570.0 -2590.0 -2610.0 -2630.0 -2650.0 -2670.0 -2690.0 -2710.0 -2730.0 -2750.0 -2770.0 -2790.0 -2810.0 -2830.0 -2850.0 -2870.0 -2890.0 -2910.0 -2930.0 -2950.0 -2970.0 -2990.0 -3010.0 -3030.0 -3050.0 -3070.0 -3090.0 -3110.0 -3130.0 -3150.0 -3170.0 -3190.0 -3210.0 -3230.0 -3250.0 -3270.0 -3290.0 -3310.0 -3330.0 -3350.0 -3370.0 -3390.0 -3410.0 -3430.0 -3450.0 -3470.0 -3490.0 -3510.0 -3530.0 -3550.0 -3570.0 -3590.0 -3610.0 -3630.0 -3650.0 -3670.0 -3690.0 -3710.0 -3730.0 -3750.0 -3770.0 -3790.0 -3810.0 -3830.0 -3850.0 -3870.0 -3890.0 -3910.0 -3930.0 -3950.0 -3970.0 -3990.0 -4010.0 -4030.0 -4050.0 -4070.0 -4090.0 -4110.0 -4130.0 -4150.0 -4170.0 -4190.0 -4210.0 -4230.0 -4250.0
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5
15
LGDP4531
Rev 1.15
Pad # . 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 www..com 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122
PAD Name S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65
X -4270.0 -4290.0 -4310.0 -4330.0 -4350.0 -4370.0 -4390.0 -4410.0 -4430.0 -4450.0 -4470.0 -4490.0 -4510.0 -4530.0 -4550.0 -4570.0 -4590.0 -4610.0 -4630.0 -4650.0 -4670.0 -4690.0 -4710.0 -4730.0 -4750.0 -4770.0 -4790.0 -4810.0 -4830.0 -4850.0 -4870.0 -4890.0 -4910.0 -4930.0 -4950.0 -4970.0 -4990.0 -5010.0 -5030.0 -5050.0 -5070.0 -5090.0 -5110.0 -5130.0 -5150.0 -5170.0 -5190.0 -5210.0 -5230.0 -5250.0 -5270.0 -5290.0 -5310.0 -5330.0 -5350.0 -5370.0 -5390.0 -5410.0 -5430.0 -5450.0 -5470.0 -5490.0 -5510.0 -5530.0 -5550.0 -5570.0 -5590.0 -5610.0 -5630.0 -5650.0 -5670.0 -5690.0 -5710.0 -5730.0 -5750.0 -5770.0 -5790.0 -5810.0 -5830.0 -5850.0 -5870.0 -5890.0 -5910.0 -5930.0 -5950.0 -5970.0 -5990.0
Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
Pad # . 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
PAD Name S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 TESTO35 TESTO36 VGLDMY3 G320 G318 G316 G314 G312 G310 G308 G306 G304 G302 G300 G298 G296 G294 G292 G290 G288 G286 G284 G282
X -6010.0 -6030.0 -6050.0 -6070.0 -6090.0 -6110.0 -6130.0 -6150.0 -6170.0 -6190.0 -6210.0 -6230.0 -6250.0 -6270.0 -6290.0 -6310.0 -6330.0 -6350.0 -6370.0 -6390.0 -6410.0 -6430.0 -6450.0 -6470.0 -6490.0 -6510.0 -6530.0 -6550.0 -6570.0 -6590.0 -6610.0 -6630.0 -6650.0 -6670.0 -6690.0 -6710.0 -6730.0 -6750.0 -6770.0 -6790.0 -6810.0 -6830.0 -6850.0 -6870.0 -6890.0 -6910.0 -6930.0 -6950.0 -6970.0 -6990.0 -7010.0 -7030.0 -7050.0 -7070.0 -7090.0 -7110.0 -7130.0 -7150.0 -7170.0 -7190.0 -7210.0 -7230.0 -7250.0 -7270.0 -7290.0 -7350.0 -7370.0 -7390.0 -7410.0 -7430.0 -7450.0 -7470.0 -7490.0 -7510.0 -7530.0 -7550.0 -7570.0 -7590.0 -7610.0 -7630.0 -7650.0 -7670.0 -7690.0 -7710.0 -7730.0 -7750.0 -7770.0
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5
Pad # . 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296
PAD Name G280 G278 G276 G274 G272 G270 G268 G266 G264 G262 G260 G258 G256 G254 G252 G250 G248 G246 G244 G242 G240 G238 G236 G234 G232 G230 G228 G226 G224 G222 G220 G218 G216 G214 G212 G210 G208 G206 G204 G202 G200 G198 G196 G194 G192 G190 G188 G186 G184 G182 G180 G178 G176 G174 G172 G170 G168 G166 G164 G162 G160 G158 G156 G154 G152 G150 G148 G146 G144 G142 G140 G138 G136 G134 G132 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108
X -7790.0 -7810.0 -7830.0 -7850.0 -7870.0 -7890.0 -7910.0 -7930.0 -7950.0 -7970.0 -7990.0 -8010.0 -8030.0 -8050.0 -8070.0 -8090.0 -8110.0 -8130.0 -8150.0 -8170.0 -8190.0 -8210.0 -8230.0 -8250.0 -8270.0 -8290.0 -8310.0 -8330.0 -8350.0 -8370.0 -8390.0 -8410.0 -8430.0 -8450.0 -8470.0 -8490.0 -8510.0 -8530.0 -8550.0 -8570.0 -8590.0 -8610.0 -8630.0 -8650.0 -8670.0 -8690.0 -8710.0 -8730.0 -8750.0 -8770.0 -8790.0 -8810.0 -8830.0 -8850.0 -8870.0 -8890.0 -8910.0 -8930.0 -8950.0 -8970.0 -8990.0 -9010.0 -9030.0 -9050.0 -9070.0 -9090.0 -9110.0 -9130.0 -9150.0 -9170.0 -9190.0 -9210.0 -9230.0 -9250.0 -9270.0 -9290.0 -9310.0 -9330.0 -9350.0 -9370.0 -9390.0 -9410.0 -9430.0 -9450.0 -9470.0 -9490.0 -9510.0
Y 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
16
LGDP4531
Rev 1.15
Pad # . 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 www..com 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354
PAD Name G106 G104 G102 G100 G98 G96 G94 G92 G90 G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 G64 G62 G60 G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 G10 G8 G6 G4 G2 VGLDMY4 DUMMYR9 DUMMYR10 TESTO37 TESTO38
X -9530.0 -9550.0 -9570.0 -9590.0 -9610.0 -9630.0 -9650.0 -9670.0 -9690.0 -9710.0 -9730.0 -9750.0 -9770.0 -9790.0 -9810.0 -9830.0 -9850.0 -9870.0 -9890.0 -9910.0 -9930.0 -9950.0 -9970.0 -9990.0 -10010.0 -10030.0 -10050.0 -10070.0 -10090.0 -10110.0 -10130.0 -10150.0 -10170.0 -10190.0 -10210.0 -10230.0 -10250.0 -10270.0 -10290.0 -10310.0 -10330.0 -10350.0 -10370.0 -10390.0 -10410.0 -10430.0 -10450.0 -10470.0 -10490.0 -10510.0 -10530.0 -10550.0 -10570.0 -10590.0 -10610.0 -10630.0 -10650.0 -10670.0
Y 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5 386.5 511.5
Alignment mark 1-a 1-b
X -10613.0 10613.0
Y -468.0 -468.0
17
LGDP4531
Rev 1.15
Bump Arrangement
20 21
100
www..com
S1 ~ S720 G1 ~ G320 DUMMYR TESTO VGLDMY (No. 299 ~ No. 1354)
225
25
S=2100
2
Unit:
50
20
I/O PINS (No. 1 ~ No. 298)
80
S=4000
2
Min. 70
Unit:
18
LGDP4531
Rev 1.15
Block Function
System Interface
The LGDP4531 supports 2-system high-speed interfaces: 80-system high-speed interfaces to 8-, 9-, 16-, 18-bit parallel ports and a Serial Peripheral Interface (SPI). The interface mode is selected by setting the IM[3:0] pins. The LGDP4531 has a 16-bit index register (IR); an 18-bit write-data register (WDR); and an 18-bit readdata register (RDR). The IR is the register to store index information from control registers and the www..com internal GRAM. The WDR is the register to temporarily store data to be written to control registers and the internal GRAM. The RDR is the register to temporarily store data read from the GRAM. Data from the MPU to be written to the internal GRAM are first written to the WDR and then automatically written to the internal GRAM in internal operation. Data are read via the RDR from the internal GRAM. Therefore, invalid data are read out to the data bus when the LGDP4531 read the first data from the internal GRAM. Valid data are read out after the LGDP4531 performs the second read operation. Instructions are written consecutively as the instruction execution time except starting oscillator takes 0 clock cycle. Table 2 Register Selection (80-system 8-/9-/16-/18-bit Parallel Interface) 80-system I/F WR* RD* 0 1 1 0 0 1 1 0 Function RS 0 0 1 1 Write an index to IR Read an internal status Write to control registers or the internal GRAM via WDR Read from the internal GRAM via RDR
Table 3 Register Selection (Serial Peripheral Interface) Start Byte (SPI) R/W RS 0 0 1 0 0 1 1 1 Function Write an index to IR Read an internal status Write into control registers and the internal GRAM via WDR Read from the internal GRAM via RDR
External Display Interface
The LGDP4531 supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture. When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK. In RGB interface mode, data (DB[17:0]) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data. In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal. Display data are written to the internal GRAM via the system interface. In this case, there are constraints in speed and method in writing data to the internal RAM. For details, see the "External Display Interface" section.
19
LGDP4531
Rev 1.15
The LGDP4531 allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)). The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display.
Address Counter (AC)
The address counter (AC) gives an address to the internal GRAM. When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC. As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus www..com1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM.
Graphics RAM (GRAM)
GRAM is graphics RAM storing bit-pattern data of 172,800 (240 x 320x 18bit) bytes, using 18 bits per pixel.
Grayscale Voltage Generating Circuit
The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the -correction register to display in 262,144 colors. For details, see the "-Correction Register" section.
Timing Generator
The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM. The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other.
Oscillator (OSC)
The LGDP4531 generates RC oscillation with an external oscillation resistor placed between the OSC1 and OSC2 pins. The oscillation frequency is changed according to the value of an external resistor. Adjust the oscillation frequency in accordance to the operating voltage or the frame frequency. An operating clock can be input externally. During standby mode, RC oscillation is halted to reduce power consumption. For details, see "Oscillator."
LCD Driver Circuit
The LCD driver circuit of the LGDP4531 consists of a 528-output source driver (S1 ~ S528) and a 240output gate driver (G1~G240). Display pattern data are latched when the 528th bit data are input. The latched data control the source driver and generate a drive waveform. The gate driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 528-bit source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit. The scan mode by the gate driver is set with the SM bit. These bits allow setting an appropriate scan method for an LCD module.
LCD Drive Power Supply Circuit
The LCD drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for driving an LCD.
Internal logic power supply regulator
The internal logic power supply regulator generates internal logic power supply VDD.
20
LGDP4531
Rev 1.15
GRAM Address MAP
Table 4 GRAM address and display panel position (SS = "0", BGR = "0")
S709 S710 S711 S712 S713 S714 S715 S716 S717 S718 S719 : : "138EF"H "139EF"H "13AEF"H "13BEF"H "13CEF"H "13DEF"H "13EEF"H "13FEF"H S720 S10 S11 S12 S/G pin S1 S2 S3 S4 S5 S6 S7 S8 S9 ...
GS=0 GS=1 G1 G2 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 G310 G309 G308 G307 G306 G305 G304 G303 G302 G301 : : G8 G7 G6 G5 G4 G3 G2 G1
DB[17:0] "00000"H "00100"H "00200"H "00300"H "00400"H "00500"H "00600"H "00700"H "00800"H "00900"H "00A00"H "00B00"H "00C00"H "00D00"H "00E00"H "00F00"H "01000"H "01100"H "01200"H "01300"H : : "13800"H "13900"H "13A00"H "13B00"H "13C00"H "13D00"H "13E00"H "13F00"H
DB[17:0] "00001"H "00101"H "00201"H "00301"H "00401"H "00501"H "00601"H "00701"H "00801"H "00901"H "00A01"H "00B01"H "00C01"H "00D01"H "00E01"H "00F01"H "01001"H "01101"H "01201"H "01301"H : : "13801"H "13901"H "13A01"H "13B01"H "13C01"H "13D01"H "13E01"H "13F01"H
DB[17:0] "00002"H "00102"H "00202"H "00302"H "00402"H "00502"H "00602"H "00702"H "00802"H "00902"H "00A02"H "00B02"H "00C02"H "00D02"H "00E02"H "00F02"H "01002"H "01102"H "01202"H "1302"H : : "13802"H "13902"H "13A02"H "13B02"H "13C02"H "13D02"H "13E02"H "13F02"H
DB[17:0] "00003"H "00103"H "00203"H "00303"H "00403"H "00503"H "00603"H "00703"H "00803"H "00903"H "00A03"H "00B03"H "00C03"H "00D03"H "00E03"H "00F03"H "01003"H "01103"H "01203"H "01303"H : : "13803"H "13903"H "13A03"H "13B03"H "13C03"H "13D03"H "13E03"H "13F03"H
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
DB[17:0] "000EC"H "001EC"H "002EC"H "003EC"H "004EC"H "005EC"H "006EC"H "007EC"H "008EC"H "009EC"H "00AEC"H "00BEC"H "00CEC"H "00DEC"H "00EEC"H "00FEC"H "010EC"H "011EC"H "012EC"H "013EC"H : : "138EC"H "139EC"H "13AEC"H "13BEC"H "13CEC"H "13DEC"H "13EEC"H "13FEC"H
DB[17:0] "000ED"H "001ED"H "002ED"H "003ED"H "004ED"H "005ED"H "006ED"H "007ED"H "008ED"H "009ED"H "00AED"H "00BED"H "00CED"H "00DED"H "00EED"H "00FED"H "010ED"H "011ED"H "012ED"H "013ED"H : : "138ED"H "139ED"H "13AED"H "13BED"H "13CED"H "13DED"H "13EED"H "13FED"H
DB[17:0] "000EE"H "001EE"H "002EE"H "003EE"H "004EE"H "005EE"H "006EE"H "007EE"H "008EE"H "009EE"H "00AEE"H "00BEE"H "00CEE"H "00DEE"H "00EEE"H "00FEE"H "010EE"H "011EE"H "012EE"H "013EE"H : : "138EE"H "139EE"H "13AEE"H "13BEE"H "13CEE"H "13DEE"H "13EEE"H "13FEE"H
DB[17:0] "000EF"H "001EF"H "002EF"H "003EF"H "004EF"H "005EF"H "006EF"H "007EF"H "008EF"H "009EF"H "00AEF"H "00BEF"H "00CEF"H "00DEF"H "00EEF"H "00FEF"H "010EF"H "011EF"H "012EF"H "013EF"H
www..com G3 G4
G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 : : G313 G314 G315 G316 G317 G318 G319 G320
21
LGDP4531
Rev 1.15
80-system 18-bit interface GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
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Note: n = lower eight bits of address (0 to 239) 80-system 16-bit interface GRAM data DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 DB DB DB DB DB DB DB DB 8 7 6 5 4 3 2 1
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
Note: n = lower eight bits of address (0 to 239) 80-system 16-bit interface MSB mode (2 transfers/pixel, 262k colors) TRI = "1", DFM = "0" 1 transfer GRAM data
st
2 transfer
nd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
Note: n = lower eight bits of address (0 to 239) 80-system 16-bit interface LSB mode (2 transfers/pixel, 262k colors) TRI = "1", DFM = "1" 1 transfer GRAM data
st
2 transfer
nd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
Note: n = lower eight bits of address (0 to 239)
Figure 2 GRAM data and display data: system interface (SS = "0", BGR = "0")
22
LGDP4531
Rev 1.15
80-system 9-bit interface (2 transfers, 262k colors) 1 transfer GRAM data
st
2 transfer
nd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
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Output pin
Note: n = lower eight bits of address (0 to 239) 80-system 8-bit interface or SPI (2 transfers, 65k colors) TRI = "0 1 transfer GRAM data DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
st
2 transfer DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
nd
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
Note: n = lower eight bits of address (0 to 239) 80-system 8-bit interface (3 transfers/pixel, 262k colors) TRI = "1", DFM = "0" 1 transfer GRAM data
st
2 transfer
nd
3 transfer
rd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
Note: n = lower eight bits of address (0 to 239) 80-system 8-bit interface (3 transfers/pixel, 262k colors) TRI = "1", DFM = "1" 1 transfer GRAM data
st
2 transfer
nd
3 transfer
rd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
Note: n = lower eight bits of address (0 to 239)
Figure 3 GRAM data and display data: system interface (SS = "0", BGR = "0")
23
LGDP4531
Rev 1.15
18-bit RGB interface GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
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Note: n = lower eight bits of address (0 to 239) 16-bit RGB interface GRAM data DB DB DB DB DB 17 16 15 14 13 DB DB DB DB DB DB DB DB DB DB DB 11 10 9 8 7 6 5 4 3 2 1
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
Note: n = lower eight bits of address (0 to 239) 6-bit RGB interface 1 transfer GRAM data
st
2 transfer
nd
3 transfer
rd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (3n + 1) S (3n + 2) S (3n + 3)
Note: n = lower eight bits of address (0 to 239)
Figure 4 GRAM data and display data: system interface (SS = "0", BGR = "0")
24
LGDP4531
Rev 1.15
Table 5 GRAM address and display panel position (SS = "1", BGR = "1")
S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 S709 S/G pin ... S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 : : S1
GS=0 G1 G2 G3 G4 G5
GS=1 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 G310 G309 G308 G307 G306 G305 G304 G303 G302 G301 : : G8 G7 G6 G5 G4 G3 G2 G1
DB[17:0] "00000"H "00100"H "00200"H "00300"H "00400"H "00500"H "00600"H "00700"H "00800"H "00900"H
DB[17:0] "00001"H "00101"H "00201"H "00301"H "00401"H "00501"H "00601"H "00701"H "00801"H "00901"H
DB[17:0] "00002"H "00102"H "00202"H "00302"H "00402"H "00502"H "00602"H "00702"H "00802"H "00902"H
DB[17:0] "00003"H "00103"H "00203"H "00303"H "00403"H "00503"H "00603"H "00703"H "00803"H "00903"H
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
DB[17:0]
DB[17:0]
DB[17:0]
DB[17:0]
"000EC"H "000ED"H "000EE"H "000EF"H "001EC"H "001ED"H "001EE"H "001EF"H "002EC"H "002ED"H "002EE"H "002EF"H "003EC"H "003ED"H "003EE"H "003EF"H "004EC"H "004ED"H "004EE"H "004EF"H "005EC"H "005ED"H "005EE"H "005EF"H "006EC"H "006ED"H "006EE"H "006EF"H "007EC"H "007ED"H "007EE"H "007EF"H "008EC"H "008ED"H "008EE"H "008EF"H "009EC"H "009ED"H "009EE"H "009EF"H "00AEC"H "00AED"H "00AEE"H "00AEF"H "00BEC"H "00BED"H "00BEE"H "00BEF"H "00CEC"H "00CED"H "00CEE"H "00CEF"H "00DEC"H "00DED"H "00DEE"H "00DEF"H "00EEC"H "00EED"H "00EEE"H "00EEF"H "00FEC"H "00FED"H "00FEE"H "00FEF"H "010EC"H "010ED"H "010EE"H "010EF"H "011EC"H "011ED"H "011EE"H "011EF"H "012EC"H "012ED"H "012EE"H "012EF"H "013EC"H "013ED"H "013EE"H "013EF"H : : : : : :
www..com G6
G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 : : G313 G314 G315 G316 G317 G318 G319 G320
"00A00"H "00A01"H "00A02"H "00A03"H "00B00"H "00B01"H "00B02"H "00B03"H "00C00"H "00C01"H "00C02"H "00C03"H "00D00"H "00D01"H "00D02"H "00D03"H "00E00"H "00E01"H "00E02"H "00E03"H "00F00"H "00F01"H "00F02"H "00F03"H "01000"H "01100"H "01200"H "01300"H : : "13800"H "13900"H "01001"H "01101"H "01201"H "01301"H : : "13801"H "13901"H "01002"H "01102"H "01202"H "1302"H : : "13802"H "13902"H "01003"H "01103"H "01203"H "01303"H : : "13803"H "13903"H
"138EC"H "138ED"H "138EE"H "138EF"H "139EC"H "139ED"H "139EE"H "139EF"H "13AEC"H "13AED"H "13AEE"H "13AEF"H "13BEC"H "13BED"H "13BEE"H "13BEF"H "13CEC"H "13CED"H "13CEE"H "13CEF"H "13DEC"H "13DED"H "13DEE"H "13DEF"H "13EEC"H "13EED"H "13EEE"H "13EEF"H "13FEC"H "13FED"H "13FEE"H "13FEF"H
"13A00"H "13A01"H "13A02"H "13A03"H "13B00"H "13B01"H "13B02"H "13B03"H "13C00"H "13C01"H "13C02"H "13C03"H "13D00"H "13D01"H "13D02"H "13D03"H "13E00"H "13E01"H "13E02"H "13E03"H "13F00"H "13F01"H "13F02"H "13F03"H
25
LGDP4531
Rev 1.15
80-system 18-bit interface GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
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Note: n = lower eight bits of address (0 to 239) 80-system 16-bit interface GRAM data DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 DB DB DB DB DB DB DB DB 8 7 6 5 4 3 2 1
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
Note: n = lower eight bits of address (0 to 239) 80-system 16-bit interface MSB mode (2 transfers/pixel, 262k colors) TRI = "1", DFM = "0" 1 transfer GRAM data
st
2 transfer
nd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
Note: n = lower eight bits of address (0 to 239) 80-system 16-bit interface LSB mode (2 transfers/pixel, 262k colors) TRI = "1", DFM = "1" 1 transfer GRAM data
st
2 transfer
nd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
Note: n = lower eight bits of address (0 to 239)
Figure 5 GRAM data and display data: system interface (SS = "1", BGR = "1")
26
LGDP4531
Rev 1.15
80-system 9-bit interface (2 transfers, 262k colors) 1 transfer GRAM data
st
2 transfer
nd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
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Output pin
Note: n = lower eight bits of address (0 to 239) 80-system 8-bit interface or SPI (2 transfers, 65k colors) TRI = "0" 1 transfer GRAM data DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
st
2 transfer DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
nd
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
Note: n = lower eight bits of address (0 to 239) 80-system 8-bit interface (3 transfers/pixel, 262k colors) TRI = "1", DFM = "0" 1 transfer GRAM data
st
2 transfer
nd
3 transfer
rd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
Note: n = lower eight bits of address (0 to 239) 80-system 8-bit interface (3 transfers/pixel, 262k colors) TRI = "1", DFM = "1" 1 transfer GRAM data
st
2 transfer
nd
3 transfer
rd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
Note: n = lower eight bits of address (0 to 239)
Figure 6 GRAM data and display data: system interface (SS = "1", BGR = "1")
27
LGDP4531
Rev 1.15
18-bit RGB interface GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
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Note: n = lower eight bits of address (0 to 239) 16-bit RGB interface GRAM data DB DB DB DB DB 17 16 15 14 13 DB DB DB DB DB DB DB DB DB DB DB 11 10 9 8 7 6 5 4 3 2 1
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
Note: n = lower eight bits of address (0 to 239) 6-bit RGB interface 1 transfer GRAM data
st
2 transfer
nd
3 transfer
rd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB Arrangement Output pin
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 S (720 - 3n) S (719 - 3n) S (718 - 3n)
Note: n = lower eight bits of address (0 to 239)
Figure 7 GRAM data and display data: system interface (SS = "1", BGR = "1")
28
LGDP4531
Rev 1.15
Instructions
Outline
The LGDP4531 adopts 18-bit bus architecture to interface to a high-performance microcomputer. The LGDP4531 starts internal processing after storing control information of externally sent 18-, 16-, 9-, 8-bit data in the instruction register (IR) and the data register (DR). Since internal operations of the LGDP4531 are controlled by the signals sent from the microcomputer, the register selection signal (RS), the read/write signal (R/W), and the internal 16-bit data bus signals (IB15 to IB0) are called instructions. The LGDP4531 use the 18-bit format internally for operations involving internal GRAM access. The www..com instructions of the LGDP4531 are categorized into the following groups. 1. 2. 3. 4. 5. 6. 7. 8. Specify the index of register Read a status Display control Power management Control Graphics data processing Set internal GRAM address Transfer data to and from the internal GRAM Internal grayscale -correction
Normally, the instruction for writing data to the internal GRAM is used the most often. Since the LGDP4531 can update internal GRAM address automatically as it writes data to the internal GRAM and minimize data transfer by using the window address function, there is less load on the program in the microcomputer. Since instructions are executed in 0 cycles, it is possible to write instructions consecutively.
Instruction Data Format
Note that as the following figure shows, the assignment of 16 instruction bits(IB15-0) to the data bus differs in different interface operations. Write instruction according to the data transfer format of the interface in use.
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LGDP4531
Rev 1.15
80-system 18-bit interface GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
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80-system 16-bit interface GRAM data DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 DB DB DB DB DB DB DB DB 8 7 6 5 4 3 2 1
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
80-system 9-bit interface 1 transfer GRAM data
st
2 transfer
nd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
80-system 8-bit interface or SPI (2/3 transfers) st 1 transfer GRAM data DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
2 transfer DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
nd
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Figure 8 Instruction bits
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LGDP4531
Rev 1.15
Instruction Description
The following are detailed explanations of instructions with illustrations of instruction bits (IB15-0) assigned to each interface.
Index (IR)
R/W W RS 0 IB15 IB14 IB13 IB12 IB11 IB10 * * * * * * IB9 * IB8 * IB7 ID7 IB6 ID6 IB5 ID5 IB4 ID4 IB3 ID3 IB2 ID2 IB1 ID1 IB0 ID0
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index register specifies the index (R00h - RFFh) of a control register or RAM control to be accessed using binary numbers "0000_0000" to "1111_1111". An access to the register as well as instruction bits contained in it is disabled unless its index is represented in this register.
Device code read (R00h)
R/W W R RS 1 1 IB15 IB14 IB13 IB12 IB11 IB10 * 0 * 1 * 0 * 0 * 0 * 1 IB9 * 0 IB8 * 1 IB7 * 0 IB6 * 0 IB5 * 1 IB4 * 1 IB3 * 0 IB2 * 0 IB1 * 0 IB0 1 1
The device code "4531"H is read out when reading out this register forcibly.
Driver output control (R01h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 SM IB9 0 IB8 SS IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 0 IB1 0 IB0 0
SS - Selects the shift direction of outputs from the source pins. If SS = "0", the source pins output from S1 to S720. If SS = "1", the source pins output from S720 to S1. The combination of SS and BGR bits controls the order of assigning RGB dots to the source driver pins S1 to S720. If SS = "0" and BGR = "0", RGB dots are assigned interchangeably from S1 to S720. If SS = "1" and BGR = "1", RGB dots are assigned interchangeably from S720 to S1. When changing SS or BGR bits, RAM data must be rewritten. SM - Sets gate driver assignment in combination with the GS bit according to the LC module. See "Scan mode setting".
LCD Driving Wave Control (R02h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 BC0 IB8 EOR IB7 0 IB6 0 IB5 IB4 IB3 IB2 IB1 IB0 NW[5:0]
NW[5:0] - Specify n, the number of raster-rows from 1 to 64, where alternations occurs every n+1 rasterrows when C-pattern waveform is generatd(BC0=1). EOR - When EOR=1, alternation occured by applying EOR(Exclusive OR) operatin to an odd/even frame selecting signal and n-raster-row inversion signal while a C-pattern waveform is generated(BC0=1).
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LGDP4531
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This instruction is used when liquid crystal alternation drive is not available due to combination of numbers of LCD raster-rows and the value of "x n". For details, see n-raster-row Inversion Alternating Drive. BC0 - Selects the liquid crystal drive waveform VCOM. See "Line Inversion AC Drive" for details. BC0 = 0: frame inversion waveform is selected. BC0 = 1: Line inversion waveform is selected. In either liquid crystal drive method, the polarity inversion is halted in blank periods (back and front porch periods).
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Entry Mode (R03h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 TRI DFM 0 BGR 0 0 IB9 0 IB8 0 IB7 ORG IB6 0 IB5 IB4 IB3 AM IB2 0 IB1 0 IB0 0 I/D[1:0]
The LGDP4531 modifies data sent from a microcomputer before writing them to the internal GRAM in order to write the GRAM data in high speed and reduce software processing load on the microcomputer. See "Graphics Operation Function" for details. TRI - Selects the RAM data transfer mode in 80-system 8-bit/16-bit bus interface operation. In 8-bit interface operation, TRI = 0: 16-bit RAM data is transferred in two transfers. TRI = 1: 18-bit RAM data is transferred in three transfers. In 16-bit bus interface operation, TRI = 0: 16-bit RAM data is transferred in one transfer. TRI = 1: 18-bit RAM data is transferred in two transfers. Make sure TRI = 0 when not using either 16-bit or 8-bit interface. Also, set TRI = 0 during read operation. DFM - Sets the mode of transferring data to the internal RAM when TRI = "1". See the following figures for details. Table 6 TRI 0 DFM RAM write data transfer via serial peripheral interface (SPI) SPI (2 transfers/pixel) - 65k colors available *
1st transfer GRAM D15 D14 D13 D12 D11 D10 D9 Data 2nd transfer D8 D7 D6 D5 D4 D3 D2 D1 D0
RGB Assign
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1
0
SPI (3 transfers/pixel) - 262k colors available
1st transfer 2nd transfer GRAM D23 D22 D21 D20 D19 D18 D15 D14 D13 D12 D11 D10 D7 Data 3rd transfer D6 D5 D4 D3 D2
RGB Assign
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1
1
Setting disabled
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LGDP4531
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Table 7 TRI 0 DFM RAM write data transfer via 8-bit interface 80-system 8-bit interface (2 transfers/pixel) - 65k colors *
GRAM Data DB 17 DB 16 DB 15 1st transfer DB DB DB 14 13 12 DB 11 DB 10 DB 17 DB 16 DB 15 2nd transfer DB DB DB 14 13 12 DB 11 DB 10
RGB Assign
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
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1
0
80-system 8-bit interface (3 transfers/pixel) - 262k colors
GRAM Data 1st DB DB 11 10 DB 17 DB 16 DB 15 2nd transfer DB DB DB 14 13 12 DB 11 DB 10 DB 17 DB 16 DB 15 3rd transfer DB DB DB 14 13 12 DB 11 DB 10
RGB Assign
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1
1
80-system 8-bit interface (3 transfers/pixel) - 262k colors
GRAM Data DB 17 DB 16 1st transfer DB DB DB 15 14 13 DB 12 DB 17 DB 16 2nd transfer DB DB DB 15 14 13 DB 12 DB 17 DB 16 3rd transfer DB DB DB 15 14 13 DB 12
RGB Assign
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Table 8 TRI 0 DFM RAM write data transfer via 16-bit interface 80-system 16-bit interface (1 transfers/pixel) - 65k colors *
GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
RGB Assign
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1
0
80-system 16-bit interface MSB mode(2 transfers/pixel) - 262k colors available
GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 1st transfer DB DB DB 10 8 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 2nd DB DB 17 16
RGB Assign
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1
1
80-system 16-bit interface LSB mode(2 transfers/pixel) - 262k colors available
GRAM Data 1st DB DB 2 1 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 2nd transfer DB DB DB 10 8 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
RGB Assign
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
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LGDP4531
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BGR - Reverses the order of RGB dots to BGR when writing 18-bit pixel data to the internal GRAM. Note that the orders of RGB dots in both WM[17:0] and CP[17:0] bits are automatically changed upon setting BGR = "1". ORG - Moves the origin of a window address area in combination with the ID setting. This function is enabled when writing data within the window address area. I/D[1:0] - The address counter is automatically incremented by 1 as writing data to the internal GRAM when I/D[1:0] = "1". The address counter is automatically decremented by 1 as writing data to the internal GRAM when I/D[1:0] = "0". The increment/decrement can be set separately to each upper (AD[15:8]) / lower (AD[7:0]) byte of address. The transition direction of address (vertical/horizontal) www..comwhen writing data to the internal GRAM is set with the AM bit. AM - Sets the direction of automatically updating address for writing data to the internal RAM in the address counter (AC). When AM = "0", the address is updated in horizontal writing direction. When AM = "1", the address is updated in vertical writing direction. When a window address area is set, data are written only to the GRAM area specified with window address in the writing direction set with I/D[1:0] and AM bits.
ORG=0 ID[1:0] = "00" Horizontal : Decrement Vertiacal : Decrement ID[1:0] = "01" Horizontal : Increment Vertiacal : Decrement ID[1:0] = "10" Horizontal : Decrement Vertiacal : Increment
17'h00000
ID[1:0] = "11" Horizontal : Increment Vertiacal : Increment
AM='0' Horizontal
17'h13FEF
AM='1' Vertical
Figure 9 Automatic address update (ORG=0, AM, ID)
ID[1:0] = "00" Horizontal : Decrement Vertiacal : Decrement
17'h00000
ORG=1
ID[1:0] = "01" Horizontal : Increment Vertiacal : Decrement
17'h00000
ID[1:0] = "10" Horizontal : Decrement Vertiacal : Increment
ID[1:0] = "11" Horizontal : Increment Vertiacal : Increment
AM='0' Horizontal
S
17'h13FEF
S
17'h13FEF
AM='1' Vertical
Figure 10 Automatic address update (ORG=1, AM, ID)
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LGDP4531
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Resizing Control (R04h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 IB8 IB7 0 IB6 0 IB5 IB4 IB3 0 IB2 0 IB1 IB0 RCV[1:0] RCH[1:0] RSZ[1:0]
RSZ[1:0] - Sets the resizing factor. When the RSZ bits are set for resizing, the LGDP4531 writes the data of the resized image in both horizontal and vertical directions according to the resizing factor on the internal GRAM. See "Resizing fuction".
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RCH[1:0] - Sets the number of pixels made as the remainder in horizontal direction as a result of resizing a picture. By specifying the number of remainder pixels with RCH bits, the data can be transferred without taking the reminder pixels into consideration. Make sure that RCH = 2'h0 when not using the resizing function (RSZ=2'h0) or there are no remainder pixels. RCV[1:0] - Sets the number of pixels made as the remainder in vertical direction as a result of resizing a picture. By specifying the number of remainder pixels with RCV bits, the data can be transferred without taking the reminder pixels into consideration. Make sure that RCV = 2'h0 when not using the resizing function (RSZ=2'h0) or there are no remainder pixels. Table 9 RSZ[1:0] 2'h0 2'h1 2'h2 2'h3 Table 10 RCH[1:0] 2'h0 2'h1 2'h2 2'h3 Table 11 RCV[1:0] 2'h0 2'h1 2'h2 2'h3 Number of remainder Pixels in Vertical Direction 0 pixel 1 pixel 2 pixels 3 pixels Number of remainder Pixels in Horizontal Direction 0 pixel 1 pixel 2 pixels 3 pixels Resizing scale No resizing ( x1) x 1/2 Setting disabled x 1/4
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LGDP4531
Rev 1.15
Display Control 1 (R07h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 PTDE[1:0] 0 0 IB9 0 IB8 BASEE IB7 0 IB6 0 IB5 IB4 IB3 IB2 0 IB1 IB0 GON DTE COL D[1:0]
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D[1:0] - A graphics display appears on the screen when D[1] = "1", and is turned off upon setting D[1] = "0". When setting D[1] = "0", the graphics display data are retained in the internal GRAM and the display appears instantly on the screen upon setting D[1] to "1". When the D[1] bit is "0", i.e. while no display is shown on the screen, all source outputs are at the GND level to reduce charging/discharging current on liquid crystal cells, which is generated during liquid crystal AC drive. When the display is turned off by setting D[1:0] = 2'h1, the LGDP4531 continues internal display operation. When the display is turned off by setting D[1:0] = 2'h0, the LGDP4531's internal display operation is halted completely. In combination with GON bit, the D[1:0] bits control ON/OFF of graphics display. For details, see "Instruction setting". Table 12 D[1:0] 2'h0 2'h1 2'h2 BASEE Source Output (S1-720) FMARK signal Internal Operation * GND Halt Halt * GND Operation Operation * Non-display Operation Operation 0 Non-display Operation Operation 2'h3 1 Base-image display Operation Operation Notes: 1. The data write operation from the microcomputer is not affected by the setting in the D[1:0] bits. 2. The PTS bits set the source output level for "non-lit display"
COL - When COL = "1", the 8-color display mode is selected. For details, see the "8-color Display Mode" section. The 8-color display mode is not available in external interface mode. Table 13 COL 1'h0 1'h1 Operating amplifier 64 2 Display color 262,144 8
Note: When COL=1, do not write the data corresponding to the grayscales, for which the operation of amplifier is halted. GON, DTE - The combination of settings in GON and DTE bits sets the output level form gate lines(G1G320). When GON=0, the Vcom output level becomes the GND level. Table 14 GON 0 0 1 1 DTE 0 1 0 1 G1-G320 VGH VGH VGL VGH/VGL
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LGDP4531
Rev 1.15
BASEE - Base image display enable bit. BASEE = 0 : No base image is displayed. The LGDP4531 drives liquid crystal at no-display level or shows only partial images on the screen. BASEE = 1 : A base image is displayed on the screen. The D[1:0] setting has precedence over the BASEE setting. PTDE[1:0] - PTDE[0] is the display enable bit of partial image 1. PTDE[1] is the display enable bit of partial image 2. When PTDE[1]/[0]=0, the partial image is turned off and only base image is displayed on the screen. When PTDE[1]/[0]= 1, the partial image is displayed on the screen. In this case, turn off the base image by setting BASEE = 0.
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Display Control 2 (R08h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 IB9 IB8 IB7 0 IB6 0 IB5 0 IB4 0 IB3 IB2 IB1 IB0 FP[3:0] BP[3:0]
FP[3:0]/BP[3:0] - Sets the blank period made at the beginning and the end of a display (front porch and back porch, respectively). The FP[3:0] and BP[3:0] bits specify the number of lines for the front and back porch periods, respectively. In setting, be sure: BP + FP 16 lines FP 2 lines BP 2 lines In external display interface mode, a back porch (BP) period starts on the falling edge of the VSYNC signal, followed by a display operation period. After driving the number of lines set with NL bits, a front porch period starts. After the front porch period, a blank period continues until the next input of VSYNC signal. Table 15 FP[3:0]/BP[3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF Number of lines for the front/back porches Setting disabled Setting disabled 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines 11 lines 12 lines 13 lines 14 lines Setting disabled
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LGDP4531
Rev 1.15
VSYNC Back porch
Display area
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Front porch Note: The output timing to the LCD is delayed by a 2-line period from the input of synchronizing signal.
Figure 11 Back/front porches Set the BP[3:0], FP[3:0] bits as follows in each operation mode. Table 16 Internal clock operation RGB interface VSYNC interface BP 2 lines BP 2 lines BP 2 lines FP 2 lines FP 2 lines FP 2 lines FP + BP 16 lines FP + BP 16 lines FP + BP = 16 lines
Display Control 3 (R09h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 IB9 PTS[2:0] IB8 IB7 0 IB6 0 IB5 IB4 IB3 IB2 IB1 IB0 PTG[1:0] ISC[3:0]
ISC[3:0] - Set the interval of scan when PTG[1:0] sets the interval scan. The scan cycle is defined by n frame periods, where n is an odd number from 3 to 31. The polarity of liquid crystal is inverted in the same cycle as the interval scan. Table 17 ISC[3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF Scan cycle Setting disabled 3 frames 5 frames 7 frames 9 frames 11 frames 13 frames 15 frames 17 frames 19 frames 21 frames 23 frames 25 frames 27 frames 29 frames 31 frames Time for interval when(fFLM)=60Hz 50ms 84ms 117ms 150ms 184ms 217ms 251ms 284ms 317ms 351ms 384ms 418ms 451ms 484ms 518ms
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LGDP4531
Rev 1.15
PTG[1:0] - Set the scan mode in non-display area, which is made between partial display periods of the first and the second images, or turning off both base and partial images(full-screen non display). The setting is commonly applied to all non-display drive period. Table 18 PTG[1:0] 2'h0 2'h1 www..com2'h2 2'h3 Gate drive operation In non-display area Normal scan Setting disabled Interval scan Setting disabled Source output level In non-display area PTS[2:0] setting PTS[2:0] setting Vcom output VcomH/VcomL amplitude VcomH/VcomL amplitude -
Note: Select frame-inversion AC drive when setting interval scan. PTS[2:0] - Set the source output in non-display drive period. Table 19 Source output level Grayscale amplifier Step-up clock In operation frequency Positive polarity Negative polarity 3h0 V63 V0 V0 to V63 Register setting(DC0,DC1) 3h1 Setting disabled Setting disabled 3h2 GND GND V0 to V63 Register setting(DC0,DC1) 3h3 Hi-Z Hi-Z V0 to V63 Register setting(DC0,DC1) 3'h4 V63 V0 V0 and V63 1/2 the frequency set with DC0,DC1 3'h5 Setting disabled Setting disabled 3'h6 GND GND V0 and V63 1/2 the frequency set with DC0,DC1 3'h7 Hi-Z Hi-Z V0 and V63 1/2 the frequency set with DC0,DC1 Notes: 1.The gate output level in non-display drive period is controlled by the PTG setting(off-scan mode). PTS[2:0]
Display Control 4 (R0Ah)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 0 IB8 0 IB7 0 IB6 0 IB5 0 IB4 0 IB3 FMARKOE IB2 IB1 FMI[2:0] IB0
FMI[2:0] - Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate. FMARKOE - When FMARKOE=1, the LGDP4531 starts outputting FMARK signal from the FMARK pin in the output interval set with the FMI[2:0] bits. See "FMARK" for details. Table 20 FMI[2:0] 3'h0 3'h1 3'h3 3'h5 Others settings Output interval 1 frame 2frame 4 frame 6 frame Setting disabled
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LGDP4531
Rev 1.15
External Display Interface Control 1 (R0Ch)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 ENC[1:0] 0 0 IB9 0 IB8 RM IB7 0 IB6 0 IB5 IB4 IB3 0 IB2 0 IB1 IB0 DM[1:0] RIM[1:0]
ENC[1:0] - Sets the RAM data write cycle in RGB interface mode. Table 21 ENC[1:0] bits ENC[1:0] www..com2'h00 2'h01 2'h10 2'h11 RAM data write cycle Write data to RAM every frame cycle Setting disabled Write data to RAM every 2 frame cycles Write data to RAM every 4 frame cycles
RM - Selects the interface to access the LGDP4531's internal GRAM. The RAM access is possible only via the interface selected with the RM bit. Set RM to "1" when writing display data via the RGB interface. The LGDP4531 allows for setting the RM bit not constrained by the mode used for the display operation. This means it is possible to rewrite display data via a system interface by setting RM = "0" even while display operations are performed via the RGB interface. Table 22 RM bit RM 1'h0 1'h1 Interface for RAM access System interface/VSYNC interface RGB interface
RIM[1:0] - Selects one of the following RGB interface modes when the RGB interface mode is selected with the RM and DM bits. Make this setting before display operation via external display interface. Do not make changes to the setting during display operation. Table 23 RIM[1:0] bits RIM[1:0] 2'h00 2'h01 2'h10 2'h11 RGB interface mode 18-bit RGB interface (1 transfer/pixel) 16-bit RGB interface (1 transfer/pixel) 6-bit RGB interface (3 transfers/pixel) Setting disabled
DM[1:0] - Sets the display operation mode. By setting DM[1:0] as follows, it is possible to switch between the internal clock operation mode and the external display interface mode. Do not switch between different external interface modes (RGB interface and VSYNC interface). Table 24 DM[1:0] bits DM[1:0] Display operation mode 2'h00 Internal clock operation 2'h01 RGB interface 2'h10 VSYNC interface 2'h11 Setting disabled Notes: 1. Instructions are set only via the system interface.
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LGDP4531
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2.
Be sure that data transfer and dot clock input are performed in units of RGB dots in 6-bit RGB interface mode.
As the following table, the optimum interface for the state of display can be selected by setting the external display interface mode. Table 25 Display State Still pictures
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Moving pictures Rewrite still picture area while display moving pictures Moving pictures Notes: 1. 2. 3. 4.
Operation mode Internal clock operation RGB interface (1) RGB interface (2) VSYNC interface
RAM access (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0)
Display mode (DM) Internal clock operation (DM = 00) RGB interface (DM = 01) RGB interface (DM = 01) VSYNC interface (DM = 10)
Instructions are set only via the system interface. The RGB-I/F and the VSYNC-I/F are not used simultaneously. Do not make changes to the RGB-I/F mode setting (RIM) while the RGB I/F is in operation. See the "External Display Interface" section for the flowcharts to follow when switching from one mode to another.
Internal clock operation mode
All display operations are synchronized with the signals generated from the internal operating clock in this mode. None of inputs via the external display interface are valid. The internal RAM is accessible only via the system interface.
RGB interface mode (1)
In RGB interface mode, display operations are synchronized with the frame synchronizing signal (VSYNC), the line synchronizing signal (HSYNC), and the dot clock (DOTCLK). These signals must be supplied through a display period using the RGB interface. Display data are transferred in units of pixels via the DB[17:0] pins. All display data are stored in the internal RAM. The combined use of the high-speed RAM write mode and the widow address function enables not only displaying data in moving picture area and data in the internal RAM in other than the moving picture area at a time but also minimizing data transfer by transferring data only when rewriting screen. The front porch (FP) and back porch (BP) periods, and the display duration period (NL) are automatically calculated inside the LGDP4531 by internally counting the number of line synchronizing signal clocks (HSYNC) from the falling edge of the frame synchronizing signal (VSYNC). Take this into consideration when transferring RGB data via the DB[17:0] pins.
RGB interface mode (2)
The LGDP4531 enables rewriting RAM data via the system interface while the RGB interface is selected for display operation. In this case, Be sure to write RAM data while display data are not being transferred via the RGB interface (ENABLE = High). To return to the display data transfer mode via the RGB interface, change the ENABLE bit first and then set a new address (AD[15:0]) in the AC and the index register to R22h.
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LGDP4531
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VSYNC interface mode
In VSYNC interface mode, internal display operations are synchronized with the frame synchronizing signal (VSYNC). In this mode, a moving picture can be displayed via the system interface by writing data to the internal RAM at more than the minimum speed from the falling edge of frame synchronizing signal (VSYNC). In this case, there are constraints in the RAM writing speed and method. For details, see "External Display Interface". No external signal input except VSYNC input is accepted in VSYNC interface mode. The timings and durations of front porch (FP), back porch (BP) periods and display duration period (NL) www..comare automatically calculated from the falling edge of the frame synchronization signal (VSYNC) according to the instructions set in the relevant registers.
Frame Maker Position (R0Dh)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 0 IB8 IB7 IB6 IB5 IB4 FMP[8:0] IB3 IB2 IB1 IB0
FMP[8:0] - Sets the output position of frame cycle signal (frame maker). When FMP[8:0] = 9'h000, a high-active pulse FMARK is output at the start of back porch period for 1H period (IOVcc-IOGND amplitude signal). FMARK can be used as a trigger signal for frame synchronous write operation. See "FMARK" for details. Make sure 9'h000 <=FMP <= BP+NL+FP Table 26 FMP[8:0] 9'h000 9'h001 9'h002 : 9'h14D 9'h14E 9'h14F FMARK output position 0th line 1st line 2nd line : 333rd line 334th line 335th line
External Display Interface Control 2 (R0Fh)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 0 IB8 0 IB7 0 IB6 0 IB5 0 IB4 IB3 IB2 0 IB1 EPL IB0 DPL VSPL HSPL
DPL - Sets the signal polarity of DOTCLK pin. DPL = 0 : input data on the rising edge of DOTCLK DPL = 1 : input data on the falling edge of DOTCLK EPL - Sets the signal polarity of ENABLE pin. EPL = 0 : writes data DB[17:0] when ENABLE = 0 and disables data write operation when ENABLE = 1. EPL = 1 : writes data DB[17:0] when ENABLE = 1 and disables data write operation when ENABLE = 0.
42
LGDP4531
Rev 1.15
HSPL - Sets the signal polarity of HSYNC pin. HSPL = 0 : Low active HSPL = 1 : High active VSPL - Sets the signal polarity of VSYNC pin. VSPL = 0 : Low active VSPL = 1 : High active
Power Control 1 (R10h)
www..com R/W
W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 SAP[2:0] IB9 IB8 IB7 0 IB6 IB5 AP[2:0] IB4 IB3 IB2 IB1 IB0 0 BT[3:0] DK DSTB SLP
SLP - When SLP = 1, the LGDP4531 enters the sleep mode. In sleep mode, the internal display operation except RC oscillation is halted to reduce power consumption. No change of GRAM data or instruction is accepted in sleep mode. The GRAM data and the instruction bits remain unchanged. DSTB - When DSTB = 1, the LGDP4531 enters the deep standby mode. In deep standby mode, the internal logic power supply is turned off to reduce power consumption. The GRAM data and the instruction bit setting are destroyed and must be reset after exiting deep standby mode. DK - Activates DDVDH. When DK = 0, DDVDH activates at the same timing as VGH. When DK = 1, DDVDH activates separately from VGH. Table 27 DK 1'h0 1'h1 Step-up Cycle in Step-up Circuit 1 Startup DDVDH simultaneously with VGH. Startup step-up circuit 1 (VLOUT1 output) according to AP[2:0] Halt step-up circuit 1 (VLOUT1). (Default)
AP[2:0] - Adjusts the constant current in the operation amplifier circuit in the LCD power supply circuit. The larger constant current enhances the drivability of the LCD, but it also increases the current consumption. Adjust the constant current taking the trade-off into account between the display quality and the current consumption. In no-display period, set AP[2:0]=3'h0 to halt the operational amplifier circuits and the step-up circuits to reduce current consumption. Adjust the amount of fixed current from the fixed-current source in the internal operational amplifier circuit. VGH operates when AP is not 000. Complete setting AP before setting PON = 1. (While setting PON = 1, setting of AP bit cannot be changed.) For the details of sequences, refer to Flow of "Power Supply Setting".
43
LGDP4531
Rev 1.15
Table 28 AP[2:0] LCD power supply circuits Grayscale voltage generating circuit 3'h0 Halt operation Halt operation 3'h1 Setting disabled Setting disabled 3'h2 Normal operation 0.5 3'h3 Normal operation 0.75 3'h4 Normal operation 1 3'h5 Normal operation 1.25 3'h6 Normal operation 1.5 www..com 3'h7 Setting disabled Setting disabled Note: In this table, the constant current in operational amplifiers is shown by the ratio to the constant current when AP[1:0] is set to 2'h3. BT[3:0] - Sets the factor used in the step-up circuits. Use an optimal step-up factor for the voltage in use. To reduce power consumption, set a smaller factor. Table 29 Step up factor and output voltage level BT[3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 DDVDH x 3 [x 6] 4'h7 4'h8~ 4'hF Note: Setting disabled 1. The step-up factor from Vci1 are shown in the brackets [ ]. 2. Connect capacitors where required when using DDVDH, VGH, VGL voltages. 3. Set the following voltages within the respective ranges: DDVDH = 6.0V(max.), VGH = 15.0V (max.) and VGL = -12.5V (max.) -(Vci1 + DDVDH) [x -3] DDVDH x 4 [x 8] DDVDH VGH VGL Capacitor connection Pins -(Vci1 + DDVDH x 2) VLOUT1, VLOUT2, VLOUT3, [x -5] C11, C12, C13, C21, C22, C23 -(DDVDH x 2) [x -4] -(Vci1 + DDVDH) [x -3] VLOUT1, VLOUT2, VLOUT3, C11, C12, C21, C22, C23 VLOUT1, VLOUT2, VLOUT3, C11, C12, C13, C21, C22, C23
Vci1 x 2 [x 2]
-(Vci1 + DDVDH x 2) VLOUT1, VLOUT2, VLOUT3, [x -5] C11, C12, C13, C21, C22, C23 Vci1 + DDVDH x 3 -(DDVDH x 2) [x 7] [x -4] -(Vci1 + DDVDH) [x -3] -(DDVDH x 2) [x -4] VLOUT1, VLOUT2, VLOUT3, C11, C12, C21, C22, C23 VLOUT1, VLOUT2, VLOUT3, C11, C12, C13, C21, C22, C23 VLOUT1, VLOUT2, VLOUT3, C11, C12, C21, C22 VLOUT1, VLOUT2, VLOUT3, C11, C12, C13, C21, C22
44
LGDP4531
Rev 1.15
SAP[2:0] - Adjust the constant current for the operational amplifer circuit in the source driver. A larger constant current stabilizes the operational ampilifer circuit, but current consumption increases. Adjust the constant current taking the display quality-current consumprion trade-off into account. During a period showing no display, set SAP = 0 to halt the operational amplifier circuit to reduce current consumption. Table 30 SAP[2:0] 3'h0 3'h1 www..com3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 Constant current (ratio to 3) Halt operational amplifier Constant current (ratio to 3) : 0.65 Constant current (ratio to 3) : 0.8 Constant current (ratio to 3) : 1.00 Constant current (ratio to 3) : 1.35 Constant current (ratio to 3) : 1.60 Setting disabled Setting disabled
Power Control 2 (R11h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 IB9 IB8 IB7 0 IB6 IB5 DC0[2:0] IB4 IB3 0 IB2 IB1 VC[2:0] IB0 DC1[2:0]
Table 31 Step-up frequency (Step-up Circuit 1) DC0[2:0] Step-up circuit 1 : step-up frequency (fDCDC1) 3'h0 fosc/4 3'h1 fosc/8 3'h2 fosc/16 3'h3 fosc/32 3'h4 fosc/64 3'h5 fosc/2 3'h6 Halt step-up circuit 1 3'h7 fosc/1 Note : Make sure to set DC0 and DC1 to maintain fDCDC1 fDCDC2 . Table 32 Step-up frequency (Step-up Circuit 2) DC1[2:0] Step-up circuit 2 : step-up frequency (fDCDC2) 3'h0 fosc/64 3'h1 fosc/128 3'h2 fosc/256 3'h3 fosc/512 3'h4 fosc/1024 3'h5 fosc/32 3'h6 Halt step-up circuit 2 3'h7 fosc/16 Note : Make sure to set DC0 and DC1 to maintain fDCDC1 fDCDC2 .
45
LGDP4531
Rev 1.15
Table 33 VciOUT output level VC[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 www..com3'h6 3'h7 VciOUT (Reference Voltage) (Vci1 Voltage) 1.00 x VciLVL 0.92 x VciLVL 0.90 x VciLVL 0.87 x VciLVL 0.85 x VciLVL 0.83 x VciLVL 0.73 x VciLVL Setting disabled
Power Control 3 (R12h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 0 IB8 0 IB7 0 IB6 0 IB5 0 IB4 PON IB3 IB2 IB1 IB0 VRH[3:0]
VRH[3:0] - Sets the factor to generate VREG1OUT from VciLVL. Table 34 VREG1OUT VRH[3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF VREG1OUT Voltage VciOUT x 1.27 VciOUT x 1.32 VciOUT x 1.37 VciOUT x 1.42 VciOUT x 1.47 VciOUT x 1.52 VciOUT x 1.57 Setting disabled Setting disabled VciOUT x 1.62 VciOUT x 1.67 VciOUT x 1.72 VciOUT x 1.77 VciOUT x 1.82 VciOUT x 1.87 VciOUT x 1.92
Note: Set the VC and VRH bits to maintain the VREG1OUT voltage at (DDVDH - 0.5) V or less. PON - Controls the operation to generate VLOUT3. In setting the PON bit, follows the power-supply startup sequence. PON = 0 : Halts the step-up operation to generate VLOUT3. PON = 1 : Starts the step-up operation to generate VLOUT3.
46
LGDP4531
Rev 1.15
Power Control 4 (R13h)
R/W W RS 1 IB15 IB14 0 0 IB13 VCOMG IB12 IB11 IB10 VDV[4:0] IB9 IB8 IB7 0 IB6 IB5 IB4 IB3 IB2 IB1 IB0 VCM[6:0]
VCM[6:0] - Sets the VcomH level (the higher voltage of Vcom alternating drive). VCM[6:0] specifies the voltage by VREG1OUT x n, where n is a discrete number from 0.400 to 0.875. To halt internal volume and adjust VcomH with an external resistor from VcomR, set VCM[6:0] = "1111111". Table 35
VCM VcomH VCM [6:0] 7'h20 7'h21 7'h22 7'h23 7'h24 7'h25 7'h26 7'h27 7'h28 7'h29 7'h2A 7'h2B 7'h2C 7'h2D 7'h2E 7'h2F 7'h30 7'h31 7'h32 7'h33 7'h34 7'h35 7'h36 7'h37 7'h38 7'h39 7'h3A 7'h3B 7'h3C 7'h3D 7'h3E 7'h3F VcomH VCM [6:0] 7'h40 7'h41 7'h42 7'h43 7'h44 7'h45 7'h46 7'h47 7'h48 7'h49 7'h4A 7'h4B 7'h4C 7'h4D 7'h4E 7'h4F 7'h50 7'h51 7'h52 7'h53 7'h54 7'h55 7'h56 7'h57 7'h58 7'h59 7'h5A 7'h5B 7'h5C 7'h5D 7'h5E 7'h5F VcomH VCM [6:0] 7'h60 7'h61 7'h62 7'h63 7'h64 7'h65 7'h66 7'h67 7'h68 7'h69 7'h6A 7'h6B 7'h6C 7'h6D 7'h6E 7'h6F 7'h70 7'h71 7'h72 7'h73 7'h74 7'h75 7'h76 7'h77 7'h78 7'h79 7'h7A 7'h7B 7'h7C 7'h7D 7'h7E 7'h7F VcomH
www..com [6:0]
7'h00 7'h01 7'h02 7'h03 7'h04 7'h05 7'h06 7'h07 7'h08 7'h09 7'h0A 7'h0B 7'h0C 7'h0D 7'h0E 7'h0F 7'h10 7'h11 7'h12 7'h13 7'h14 7'h15 7'h16 7'h17 7'h18 7'h19 7'h1A 7'h1B 7'h1C 7'h1D 7'h1E 7'h1F VREG1OUT x 0.400 VREG1OUT x 0.405 VREG1OUT x 0.410 VREG1OUT x 0.415 VREG1OUT x 0.420 VREG1OUT x 0.425 VREG1OUT x 0.430 VREG1OUT x 0.435 VREG1OUT x 0.440 VREG1OUT x 0.445 VREG1OUT x 0.450 VREG1OUT x 0.455 VREG1OUT x 0.460 VREG1OUT x 0.465 VREG1OUT x 0.470 VREG1OUT x 0.475 VREG1OUT x 0.480 VREG1OUT x 0.485 VREG1OUT x 0.490 VREG1OUT x 0.495 VREG1OUT x 0.500 VREG1OUT x 0.505 VREG1OUT x 0.510 VREG1OUT x 0.515 VREG1OUT x 0.520 VREG1OUT x 0.525 VREG1OUT x 0.530 VREG1OUT x 0.535 VREG1OUT x 0.540 VREG1OUT x 0.545 VREG1OUT x 0.550 VREG1OUT x 0.555
VREG1OUT x 0.560 VREG1OUT x 0.565 VREG1OUT x 0.570 VREG1OUT x 0.575 VREG1OUT x 0.580 VREG1OUT x 0.585 VREG1OUT x 0.590 VREG1OUT x 0.595 VREG1OUT x 0.600 VREG1OUT x 0.605 VREG1OUT x 0.610 VREG1OUT x 0.615 VREG1OUT x 0.620 VREG1OUT x 0.625 VREG1OUT x 0.630 VREG1OUT x 0.635 VREG1OUT x 0.640 VREG1OUT x 0.645 VREG1OUT x 0.650 VREG1OUT x 0.655 VREG1OUT x 0.660 VREG1OUT x 0.665 VREG1OUT x 0.670 VREG1OUT x 0.675 VREG1OUT x 0.680 VREG1OUT x 0.685 VREG1OUT x 0.690 VREG1OUT x 0.695 VREG1OUT x 0.700 VREG1OUT x 0.705 VREG1OUT x 0.710 VREG1OUT x 0.715
VREG1OUT x 0.720 VREG1OUT x 0.725 VREG1OUT x 0.730 VREG1OUT x 0.735 VREG1OUT x 0.740 VREG1OUT x 0.745 VREG1OUT x 0.750 VREG1OUT x 0.755 VREG1OUT x 0.760 VREG1OUT x 0.765 VREG1OUT x 0.770 VREG1OUT x 0.775 VREG1OUT x 0.780 VREG1OUT x 0.785 VREG1OUT x 0.790 VREG1OUT x 0.795 VREG1OUT x 0.800 VREG1OUT x 0.805 VREG1OUT x 0.810 VREG1OUT x 0.815 VREG1OUT x 0.820 VREG1OUT x 0.825 VREG1OUT x 0.830 VREG1OUT x 0.835 VREG1OUT x 0.840 VREG1OUT x 0.845 VREG1OUT x 0.850 VREG1OUT x 0.855 VREG1OUT x 0.860 VREG1OUT x 0.865 VREG1OUT x 0.870 VREG1OUT x 0.875
VREG1OUT x 0.880 VREG1OUT x 0.885 VREG1OUT x 0.890 VREG1OUT x 0.895 VREG1OUT x 0.900 VREG1OUT x 0.905 VREG1OUT x 0.910 VREG1OUT x 0.915 VREG1OUT x 0.920 VREG1OUT x 0.925 VREG1OUT x 0.930 VREG1OUT x 0.935 VREG1OUT x 0.940 VREG1OUT x 0.945 VREG1OUT x 0.950 VREG1OUT x 0.955 VREG1OUT x 0.960 VREG1OUT x 0.965 VREG1OUT x 0.970 VREG1OUT x 0.975 VREG1OUT x 0.980 Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Halt internal volume.
Note : Set the VcomH voltage from 2.5V to (DDVDH - 0.5 ) V.
47
LGDP4531
Rev 1.15
VDV[4:0] - Sets the alternating amplitudes of VCOM AC voltage. These bits amplify VCOM by from 0.6 to 1.23 times the VREG1OUT voltage. If VCOMG = 0, VDV[4:0] bits are disabled. Table 36 VDV[4:0] Vcom amplitude VDV[4:0] Vcom amplitude 5'h00 VREG1OUT x 0.60 5'h10 VREG1OUT x 1.05 5'h01 VREG1OUT x 0.63 5'h11 VREG1OUT x 1.08 5'h02 VREG1OUT x 0.66 5'h12 VREG1OUT x 1.11 5'h03 VREG1OUT x 0.69 5'h13 VREG1OUT x 1.14 VREG1OUT x 0.72 5'h14 VREG1OUT x 1.17 www..com5'h04 5'h05 VREG1OUT x 0.75 5'h15 VREG1OUT x 1.20 5'h06 VREG1OUT x 0.78 5'h16 VREG1OUT x 1.23 5'h07 VREG1OUT x 0.81 5'h17 VREG1OUT x 1.26 5'h08 VREG1OUT x 0.84 5'h18 VREG1OUT x 1.29 5'h09 VREG1OUT x 0.87 5'h19 VREG1OUT x 1.32 5'h0A VREG1OUT x 0.90 5'h1A VREG1OUT x 1.35 5'h0B VREG1OUT x 0.93 5'h1B VREG1OUT x 1.38 5'h0C VREG1OUT x 0.96 5'h1C VREG1OUT x 1.41 5'h0D VREG1OUT x 0.99 5'h1D VREG1OUT x 1.44 5'h0E VREG1OUT x 1.02 5'h1E VREG1OUT x 1.47 5'h0F Setting disabled 5'h1F VREG1OUT x 1.50 Note : Set the VcomH voltage from 2.5V to (DDVDH - 0.5 ) V. VCOMG - When VCOMG = 1, the LGDP4531 can output a negative voltage level for VCOML (1.0 ~ Vci + 0.5V max ). When VCOMG = 0, the LGDP4531 halts the amplifier for negative voltage to save power. When VCOMG = 0, the VDV[4:0] bits are disabled. In this case, adjust the amplitude of VCOM AV voltage with VCM[4:0] bits ( VCOMH setting ). Set PON = 1 before setting VCOMG = 1. When VCOMG = 1, voltage of VCOML can be set to any level, and instruction (VDV) becomes valid. VCOMG = 1 is valid when PON = 1. When COMG = 0, output of VCOML if fixed to GND level, and setting of instruction (VDV) becomes invalid. When VCOMG = 0, output of VCOML and VCL stop.
Regulator Control (R15h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 RSET 0 IB9 RI[2:0] IB8 IB7 0 IB6 IB5 RV[2:0] IB4 IB3 0 IB2 IB1 IB0 RCONT[2:0]
RCONT[2:0] - These bits control the input voltage of main bias op_amp. Table 37 RCONT[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7
Input voltage Vci x 0.25 Setting diabled Open Vci x 0.30 Setting disabled Setting disabled Vci x 0.20 Setting disabled
48
LGDP4531
Rev 1.15
RV[2:0] - These bits control the output voltage of internal logic regulator. Table 38 RV [2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 www..com3'h5 3'h6 3'h7
Vdd voltage Vci x 0.80 Vci x 0.75 Vci x 0.70 Vci x 0.65 Vci x 0.60 Vci x 0.55 Vci x 0.50 Vci x 0.45
RI[2:0] - These bits control the bias current of internal logic regulator. Table 39 RI [2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7
Constant current 0.2 0.1 2.2 3 3.2 4 5.2 6
Note : In this table, the constant current is shown by the ratio to the constant current when RI[2:0] is set to 3'h3. RSET[2:0] - These bits control the main bias.
IPS Control (R16h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 0 IB8 0 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 0 IB1 0 IB0 IPS
IPS - This bit specify the IPS mode enable signal. Table 40 IPS 1'h0 1'h1
Mode TN mode IPS mode
49
LGDP4531
Rev 1.15
Table 41 In TN mode N frame Line VCOM1 VCOM2 1 VCOML VCOML 2 VCOMH VCOMH 3 VCOML VCOML 4 VCOMH VCOMH ... ... ... 319 VCOML VCOML www..com 320 VCOMH VCOMH Table 42 In IPS mode N frame Line VCOM1 VCOM2 1 VCOML Hi-Z 2 Hi-Z VCOMH 3 VCOML Hi-Z 4 Hi-Z VCOMH ... ... ... 319 VCOML Hi-Z 320 Hi-Z VCOMH
N+1 frame VCOM1 VCOM2 VCOMH VCOMH VCOML VCOML VCOMH VCOMH VCOML VCOML ... ... VCOMH VCOMH VCOML VCOML
N+1 frame VCOM1 VCOM2 VCOMH Hi-Z Hi-Z VCOML VCOMH Hi-Z Hi-Z VCOML ... ... VCOMH Hi-Z Hi-Z VCOML
RAM Address Set (Horizontal Address) (R20h) RAM Address Set (Vertical Address) (R21h)
R/W W W RS 1 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 0 0 0 0 0 0 IB9 0 0 IB8 0 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 AD[7:0] AD[16:8]
AD[16:0] - A GRAM address set initially in the AC (Address Counter). The address in the AC is automatically updated according to the combination of AM, I/D[1:0] settings as data is written to the internal GRAM in order to write data consecutively without resetting the address in the AC. The address is not automatically updated when reading data from the internal GRAM. Note 1: In RGB interface operation (RM='1'), the address AD[16:0] is set in the address counter every frame on the falling edge of VSYNC. Note 2: In internal clock operation and VSYNC interface operation (RM='0'), the address AD[16:0] is set when executing the instruction. Table 43 AD[16:0] 17'h00000 - 17'h000EF 17'h00100 - 17'h001EF 17'h00200 - 17'h002EF : 17'h16500 - 17'h13DEF 17'h16600 - 17'h13EEF 17'h16700 - 17'h13FEF
GRAM Data Setting Bitmap data on the first line Bitmap data on the second line Bitmap data on the third line : Bitmap data on the 318th line Bitmap data on the 319th line Bitmap data on the 320th line
50
LGDP4531
Rev 1.15
Write Data to RAM (R22h)
R/W W RS 1 The bit assignment between RAM write data WD[17:0] and DB[17:0] differs according to the selected interface. WD[17:0]
WD[17:0] - The LGDP4531 write data to the internal GRAM by expanding into 18 bits internally. The data expansion fomat into 18 bits differs according to the interface. The GRAM data represents the grayscale level. The LGDP4531 automatically updates the address according to AM and I/D[1:0] as it writes data in the GRAM. In standby mode, the GRAM is not accessible. The data in 16-bit format is developed into 18 bits according to the register setting (DFM) in www..com 8-/16-bit interface operation. Note : When writing data in the GRAM via system interface while using the RGB interface, make sure that write operation via two interface do not conflict.
51
LGDP4531
Rev 1.15
Table 44 GRAM data and corresponding LCD Grayscale level GRAM data RGB Netative Positive 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 www..com 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F V63 V62 V61 V60 V59 V58 V57 V56 V55 V54 V53 V52 V51 V50 V49 V48 V47 V46 V45 V44 V43 V42 V41 V40 V39 V38 V37 V36 V35 V34 V33 V32 V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31
Grayscale level (REV = 1) Grayscale level GRAM data RGB Netative 6'h20 V31 6'h21 V30 6'h22 V29 6'h23 V28 6'h24 V27 6'h25 V26 6'h26 V25 6'h27 V24 6'h28 V23 6'h29 V22 6'h2A V21 6'h2B V20 6'h2C V19 6'h2D V18 6'h2E V17 6'h2F V16 6'h30 V15 6'h31 V14 6'h32 V13 6'h33 V12 6'h34 V11 6'h35 V10 6'h36 V9 6'h37 V8 6'h38 V7 6'h39 V6 6'h3A V5 6'h3B V4 6'h3C V3 6'h3D V2 6'h3E V1 6'h3F V0
Positive V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63
52
LGDP4531
Rev 1.15
Table 45 GRAM data and corresponding LCD Grayscale level GRAM data RGB Netative Positive 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 www..com 6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V63 V62 V61 V60 V59 V58 V57 V56 V55 V54 V53 V52 V51 V50 V49 V48 V47 V46 V45 V44 V43 V42 V41 V40 V39 V38 V37 V36 V35 V34 V33 V32
Grayscale level (REV = 0) Grayscale level GRAM data RGB Netative 6'h20 V32 6'h21 V33 6'h22 V34 6'h23 V35 6'h24 V36 6'h25 V37 6'h26 V38 6'h27 V39 6'h28 V40 6'h29 V41 6'h2A V42 6'h2B V43 6'h2C V44 6'h2D V45 6'h2E V46 6'h2F V47 6'h30 V48 6'h31 V49 6'h32 V50 6'h33 V51 6'h34 V52 6'h35 V53 6'h36 V54 6'h37 V55 6'h38 V56 6'h39 V57 6'h3A V58 6'h3B V59 6'h3C V60 6'h3D V61 6'h3E V62 6'h3F V63
Positive V31 V30 V29 V28 V27 V26 V25 V24 V23 V22 V21 V20 V19 V18 V17 V16 V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0
53
LGDP4531
Rev 1.15
Read Data from RAM (R22h)
R/W R RS 1 The bit assignment between RAM write data RD[17:0] and DB[17:0] differs according to the selected interface. RD[17:0]
RD[17:0] - 18-bit data read from the GRAM. The bit assignment between RD[17:0] and DB[17:0] (data on the data bus) differs according to the selected interface. When the LGDP4531 read data from the GRAM to the microcomputer, the first word read immediately after RAM address set is taken in the intenal read-data latch and inbalid data is sent to the data bus www..com DB[17:0]. Vaild data is sent to the data bus as the LGDP4531 reads out the second and subsequence words. When either 8-bit or 16-bit interface is selected, the LSB of R and B dot data are not read out. Note : This register is not available in RGB interface operation.
Figure 12
54
LGDP4531
Rev 1.15
Gamma Control 1-10 (R30h to R39h)
R/W W W W W W RS 1 1 1 1 1 1 1 1 1 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB9 IB8 IB7 0 0 0 0 0 0 0 0 0 0 IB6 0 0 0 0 0 0 0 0 0 0 IB5 0 0 0 0 0 0 0 0 0 0 IB4 0 0 0 0 0 0 0 0 0 0 IB3 0 0 0 0 0 0 0 0 IB2 IB1 PKP0[2:0] PKP2[2:0] PKP4[2:0] PRP0[2:0] PKN0[2:0] PKN2[2:0] PKN4[2:0] PRN0[2:0] VRP0[3:0] VRN0[3:0] IB0 PKP1[2:0] PKP3[2:0] PKP5[2:0] PRP1[2:0] PKN1[2:0] PKN3[2:0] PKN5[2:0] PRN1[2:0] VRP1[4:0] VRN1[4:0]
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W W W W
PKP5-0[2 :0] - fine-adjustment register for positive polarity PRP1-0[2 :0] - gradient-adjustment register for positive polarity VRP0[3:0],VRP1[4 :0] - amplitude-adjustment register for positive polarity PKN5-0[2 :0] - fine-adjustment register for negative polarity PRN1-0[2 :0] - gradient-adjustment register for negative polarity VRN0[3:0], VRN1[4 :0] - amplitude-adjustment register for negative polarity
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LGDP4531
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EPROM Control Register 1 (R40h)
R/W W RS 1 IB15 IB14 IB13 IB12 0 0 IB11 IB10 IB9 IB8 IB7 0 IB6 IB5 IB4 IB3 IB2 IB1 IB0 POR VPP PPROG PWE PA[1:0] PDIN[6:0]
EPROM programming control. See "EPROM Control" section.
PDIN[6:0] - Data input. This corresponds to VCM[6:0] bits of R13h. PA[1:0] - address input. This selects one of four banks of the EPROM.
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Table 46 PA[1:0] 2'h0 2'h1 2'h2 2'h3
Write Data Input PDIN[6:0] PDIN[6:0] PDIN[6:0] PDIN[6:0]
Write OPT Cell Cell[6:0] Cell[14:8] Cell[22:16] Cell[30:24]
PWE - Write enable. PPROG - Program mode enable. VPP - Power switch control for the VPP pin of the embedded EPROM. When VPP = "1", the internal VPP is set to 7.2V; otherwise it is set to 1.8V. POR - Pin for power-on rest.
EPROM Control Register 2 (R41h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 RA[1:0] VCMSEL[1:0]
EPROM programming control. See "EPROM Control" section.
VCMSEL[1:0] - With VCMSEL pin, sets VcomH level from either the register R13h or the EPROM Table 47 VCMSEL[1:0] 00 01 1X 1X
VCMSEL pin X X 0 1
VcomH Level adjustment VCM[6:0] of the register R13h EPROM data selected by RA[1:0] VCM[6:0] of the register R13h EPROM data selected by RA[1:0]
RA[1:0] - Read address input. This selects one of four banks of the EPROM.
EPROM Control Register 3 (R42h)
R/W R RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 PDOUT[6:0]
PDOUT[6:0] - EPROM Read Data output.
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LGDP4531
Rev 1.15
Window Horizontal RAM Address Start/End (R50h/R51h) Window Vertical RAM Address Start/End (R52h/R53h)
R/W W W W RS 1 1 1 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB9 0 0 0 0 IB8 0 0 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 HSA[7:0] HEA[7:0] VSA[8:0] VEA[8:0]
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HSA[7:0]/HEA[7:0] - HSA[7:0] and HEA[7:0] represent the addresses at the start and end of the window address area in horizontal direction, respectively. HSA[7:0] and HEA[7:0] specify the range on the GRAM to write data. Set HSA[7:0] and HEA[7:0] before starting RAM write operation. In setting, make sure that 8'h00 HSA < HEA 8'hEF. VSA[8:0]/VEA[8:0] - VSA[8:0] and VEA[8:0] represent the addresses at the start and end of the window address area in vertical direction, respectively. VSA[8:0] and VEA[8:0] specify the range on the GRAM to write data. Set VSA[8:0] and VEA[8:0] before starting RAM write operation. In setting, make sure that 9'h000 VSA < VEA 9'h13F.
Figure 13
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LGDP4531
Rev 1.15
Driver Output Control (R60h) Base Image Display Control (R61h) Vertical Scroll Control (R6Ah)
R/W W RS 1 1 1 IB15 IB14 IB13 IB12 IB11 IB10 GS 0 0 0 0 0 0 0 0 0 NL[5:0] 0 0 0 0 0 0 0 IB9 IB8 IB7 0 0 IB6 0 0 0 0 VL[8:0] IB5 IB4 IB3 IB2 IB1 IB0
SCN[5:0] 0 NDL VLE REV
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W W
SCN[5:0] - Specifies the gate line where the gate driver starts scan. NL[5:0] - Sets the number of lines to drive the LCD at an interval of 8lines. The GRAM address mapping is not affected by the number of lines set with NL[5:0]. The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel. Table 48 NL[5:0] 6'h00 - 6'h1C 6'h1D 6'h1E 6'h1F 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 - 6'h3F
Number of Lines Setting disabled 240 (lines) 248 256 264 272 280 288 296 304 312 320 Setting disabled
GS - Set the direction of scan by the gate driver. Set the GS bit in combination with SM and SS bits to optimize scan method to the LCD module. REV - The grayscale level corresponding to the GRAM data can be reversed by setting REV = 1. This enables the LGDP4531 to display the same image form a same set of data whether the liquid crystal panel is normally black or white. The source output level during front, back porch periods and blank periods is determined by resiger setting (PTS).
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LGDP4531
Rev 1.15
Table 49 REV GRAM Data 18'h00000 : 18'h3FFFF 18'h00000 : 18'h3FFFF Source Output Level in Display Area Positive Polarity Negative Polarity V63 : V0 V0 : V63 V0 : V63 V63 : V0
0
1
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VLE - Vertical scroll display enable bit. When VLE = 1, the LGDP4531 starts displaying the base image from the line (of the physical display) determined by setting the VL[8:0] bits. VL[8:0] represents the number of lines shifted from the first line of the physical display ( the amount of scrolling). Note that the display position of partial image is not affected by the base image scrolling. The vertical scrolling is not available in external display inteface opration. In this case, make sure to set VLE = 0. NDL - Sets the source output level in non-display lit driving periods. By setting the NDL bit, the nondisplay area can be kept lit on. Table 50 NDL 0 1 Non-display area Positive V63 V0 Negative V0 V63
VL[8:0] - Sets the amount of scrolling the base image by the number of lines. The RAM data in the start line address is displayed on the line, which is shifted from the first line of the liquid crystal panel by the number of lines set with VL[8:0]. In setting VL[8:0], make sure VL 320.
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LGDP4531
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Table 51 SCN[5:0] 6'h00 6'h01 6'h02 6'h03 6'h04 6'h05 www..com6'h06 6'h07 6'h08 6'h09 6'h0A 6'h0B 6'h0C 6'h0D 6'h0E 6'h0F 6'h10 6'h11 6'h12 6'h13 6'h14 6'h15 6'h16 6'h17 6'h18 6'h19 6'h1A 6'h1B 6'h1C 6'h1D 6'h1E 6'h1F 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 - 6'h3F Gate line No (Scan start position) SM = 0 GS = 0 GS = 1 G1 G320 G9 G312 G17 G304 G25 G296 G33 G288 G41 G280 G49 G272 G57 G264 G65 G256 G73 G248 G81 G240 G89 G232 G97 G224 G105 G216 G113 G208 G121 G200 G129 G192 G137 G184 G145 G176 G153 G168 G161 G160 G169 G152 G177 G144 G185 G136 G193 G128 G201 G120 G209 G112 G217 G104 G225 G96 G233 G88 G241 G80 G249 G72 G257 G64 G265 G56 G273 G48 G281 G40 G289 G32 G297 G24 G305 G16 G313 G8 Setting disabled Setting disabled SM = 1 GS = 0 G1 G17 G33 G49 G65 G81 G97 G113 G129 G145 G161 G177 G193 G209 G225 G241 G257 G273 G289 G305 G2 G18 G34 G50 G66 G82 G98 G114 G130 G146 G162 G178 G194 G210 G226 G242 G258 G274 G290 G306 Setting disabled
GS = 1 G320 G304 G288 G272 G256 G240 G224 G208 G192 G176 G160 G144 G128 G112 G96 G80 G64 G48 G32 G16 G319 G303 G287 G271 G255 G239 G223 G207 G191 G175 G159 G143 G127 G111 G95 G79 G63 G47 G31 G15 Setting disabled
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LGDP4531
Rev 1.15
Partial Image 1: Display Position (R80h) RAM Address (Start/End Line Address) (R81h/R82h) Partial Image 2: Display Position (R83h) RAM Address (Start/End Line Address) (R84h/R85h)
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R/W W W W W W W RS 1 1 1 1 1 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB9 0 0 0 0 0 0 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
PTDP0[8:0] PTSA0[8:0] PTEA0[8:0] PTDP1[8:0] PTSA1[8:0] PTEA1[8:0]
PTDP0[8:0] - Sets the display position of partial image 1. PTDP1[8:0] - Sets the display position of partial image 2. The display areas of the partial images 1 and 2 must not overlap each another. In setting make sure that Partial image 1 display area < Partial image 2 display area, and Coordinates of partial image 1 display position : (PTDP0, PTEA0) Coordinates of partial image 2 display position : (PTDP1, PTEA1) If PTDP0 = 9'h000, the partial image 1 is displayed from the first line of the base image. PTSA0[8:0] - Sets the start line addresses of the RAM area, respectively for the partial image 1 PTEA0[8:0] - Sets the end display position of partial image 1. PTSA1[8:0] - Sets the start line addresses of the RAM area, respectively for the partial image 2. PTEA1[8:0] - Sets the end display position of partial image 2.
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LGDP4531
Rev 1.15
Panel Interface Control 1 (R90h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 IB8 IB7 0 IB6 0 IB5 0 IB4 IB3 IB2 RTNI[4:0] IB1 IB0 DIVI[1:0]
RTNI[4:0] - Sets 1H (line) period. This setting is enabled while the LGDP4531's display operation is synchronized with internal clock. DIVI[1:0] - Sets the division ratio of the internal clock frequency. The LGDP4531's internal operation is synchronized with the frequency divided internal clock. When changing the DIVI[1:0] bits, the width of www..com the reference clock for liquid crystal panel control signals is changed.
The frame frequency can be adjusted by register setting (RTNI and DIVI bits). When changing the number of lines to drive the liquid crystal panel, adjust the frame frequency too. For details, see "Frame-Frequency Adjustment Function". The setting in DIVI[1:0] is disabled in RGB interface operation.
Frame Frequency Calculation Frame frequency = fosc/(clock cycles per line x division ratio x (active line + BP + FP)) Table 52 clocks per line (internal clock operation 1 clock = 1 OSC) RTNI[4:0] Clock per Line 5'h00 - 5'h0F Setting disabled 5'h10 64 clocks 5'h11 68 clocks 5'h12 72 clocks 5'h13 76 clocks 5'h14 80 clocks 5'h15 84 clocks 5'h16 88 clocks 5'h17 92 clocks 5'h18 96 clocks 5'h19 100 clocks 5'h1A 104 clocks 5'h1B 108 clocks 5'h1C 112 clocks 5'h1D 116 clocks 5'h1E 120 clocks 5'h1F 124 clocks
Table 53 Division ratio of the internal clock DIVI[1:0] Division Ratio Internal operation clock unit 2'h0 1/1 1 OSC 2'h1 1/2 2 OSC 2'h2 1/4 4 OSC 2'h3 1/8 8 OSC
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LGDP4531
Rev 1.15
Panel Interface Control 2 (R92h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 IB9 IB8 IB7 0 IB6 0 IB5 0 IB4 0 IB3 IB2 IB1 IB0 NOWI[2:0] EQI2[1:0] EQI1[1:0]
EQI1[1:0] - Sets equalization period. Note : when VCOML >= 0V, EQI1,EQI2 setting is diaabled.
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Table 54 EQI1[1:0] 2'h0 2'h1 2'h2 2'h3
Equalization period 0 (internal clock period see note ) 2 4 6
EQI2[1:0] - Sets equalization period. Table 55 EQI2[1:0] 2'h0 2'h1 2'h2 2'h3
Equalization period 0 (internal clock period see note ) 2 4 6
NOWI[2:0] - Sets the non-overlap period of adjacent gate outputs. The setting is enabled in display operation in synchronization with internal clock. : Table 56 NOWI[2:0] Non-overlap period 3'h0 0 (internal clock period see note ) 3'h1 4 3'h2 8 3'h3 12 3'h4 16 3'h5 20 3'h6 24 3'h7 28 Note : The internal clock is the frequency divided clock with the division ratio set with the DIVI[1:0] bits.
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LGDP4531
Rev 1.15
Panel Interface Control 3 (R93h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 0 IB8 0 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 IB1 IB0 MCPI[2:0]
MCPI[2:0] - Sets the source output timing by the number of internal clock from a reference point. The setting is enabled in display operation in synchronization with internal clock. Table 57 www..comMCPI[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7
Source output position 0 (internal clock period see note ) 4 8 12 16 20 24 28
Note: The internal clock is the frequency divided clock with the division ratio set with the DIVI[[1:0] bits. The source output position is measured from a reference point by the number of internal clock cycle.
Panel Interface Control 4 (R95h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 IB8 IB7 0 IB6 0 IB5 IB4 IB3 IB2 IB1 IB0 DIVE[1:0] RTNE[5:0]
RTNE[5:0] - Sets the number of internal clocks per 1H (line) period. Set the value that represents the number of DOTCLKs divided by the division ratio, which is input in a 1H period. DIVE[1:0] - Sets DIVE, the internal division ratio of DOTCLK. The internal operation is performed according to the clocks divided by the internal division ratio DIVE. Table 58 Division ratio of DOTCLK DIVE[1:0] Division Internal operation clock unit (DOTCLK) Ratio 18-bit, 1 transfer RGB interface DOTCLK = 5 MHz 8-bit, 3 transfer RGB interface DOTCLK = 15 MHz 2'h0 2'h1 2'h2 2'h3
Setting disabled Setting disabled
0.2 s 0.4 s 0.8 s
Setting disabled
0.2 s 0.4 s 0.8 s
1/1 1/2 1/4
1 DOTCLKs 2 DOTCLKs 4 DOTCLKs
3 DOTCLKs 6 DOTCLKs 12 DOTCLKs
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LGDP4531
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Table 59 DOTCLK per line (1H period) RTNE[5:0] DOTCLK per line (1H) 6'h00 Setting disabled 6'h01 Setting disabled 6'h02 Setting disabled 6'h03 Setting disabled 6'h04 Setting disabled 6'h05 Setting disabled 6'h06 Setting disabled www..com 6'h07 Setting disabled 6'h08 Setting disabled 6'h09 Setting disabled 6'h0A Setting disabled 6'h0B Setting disabled 6'h0C Setting disabled 6'h0E Setting disabled 6'h0E Setting disabled 6'h0F Setting disabled 6'h10 64 clocks 6'h11 68 clocks 6'h12 72 clocks 6'h13 76 clocks 6'h14 80 clocks 6'h15 84 clocks 6'h16 88 clocks 6'h17 92 clocks 6'h18 96 clocks 6'h19 100 clocks 6'h1A 104 clocks 6'h1B 108 clocks 6'h1C 112 clocks 6'h1E 116 clocks 6'h1E 120 clocks 6'h1F 124 clocks
RTNE[5:0] 6'h20 6'h21 6'h22 6'h23 6'h24 6'h25 6'h26 6'h27 6'h28 6'h29 6'h2A 6'h2B 6'h2C 6'h2E 6'h2E 6'h2F 6'h30 6'h31 6'h32 6'h33 6'h34 6'h35 6'h36 6'h37 6'h38 6'h39 6'h3A 6'h3B 6'h3C 6'h3E 6'h3E 6'h3F
DOTCLK per line (1H) 128 clocks 132 clocks 136 clocks 140 clocks 144 clocks 148 clocks 152 clocks 156 clocks 160 clocks 164 clocks 168 clocks 172 clocks 176 clocks 180 clocks 184 clocks 188 clocks 192 clocks 196 clocks 200 clocks 204 clocks 208 clocks 212 clocks 216 clocks 220 clocks 224 clocks 228 clocks 232 clocks 236 clocks 240 clocks 244 clocks 248 clocks 252 clocks
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LGDP4531
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Panel Interface Control 5 (R97h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 IB9 IB8 IB7 0 IB6 0 IB5 0 IB4 0 IB3 IB2 IB1 IB0 NOWE[3:0] EQE2[1:0] EQE1[1:0]
EQE1[1:0] - Sets equalization period. Note : when VCOML >= 0V, EQE1,EQE2 setting is disabled.
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Table 60 EQE1[1:0] 2'h0 2'h1 2'h2 2'h3
Equalization period 0 (internal clock period see note ) 8 16 24
EQE2[1:0] - Sets equalization period. Table 61 EQE2[1:0] 2'h0 2'h1 2'h2 2'h3
Equalization period 0 (internal clock period see note ) 8 16 24
NOWE[3:0] - Sets the non-overlap period of adjacent gate outputs. The settint is enabled in display operation via RGB interface. Table 62 NOWE[3:0] 4'h0 4'h1 4'h2 4'h3 4'h4 4'h5 4'h6 4'h7
Non-overlap period 0 (internal clock period see note ) 4 8 12 16 20 24 28
NOWE[3:0] 4'h8 4'h9 4'hA 4'hB 4'hC 4'hD 4'hE 4'hF
Non-overlap period 32 36 40 44 48 52 56 60
Note : 1 clock = (Number of data transfers / pixel) x DIVE (division ratio) [DOTCLK].
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LGDP4531
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Panel Interface Control 6 (R98h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 0 IB8 0 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 IB1 IB0 MCPE[2:0]
MCPE[2:0] - Sets the source output timing by the number of internal clock from a reference point. The setting is enabled in display operation via RGB interface. Table 63 MCPE[2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7
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Source output position 0 (internal clock period see note ) 4 8 12 16 20 24 28
Note : 1 clock = (Number of data transfers / pixel) x DIVE (division ratio) [DOTCLK].
Test Register 1 (RA0h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 0 IB8 TDFN IB7 0 IB6 0 IB5 0 IB4 TOSC IB3 0 IB2 0 IB1 IB0 TVCOM[1:0]
TVCOM[1:0] - Sets the Vcom output level for test. Table 64 TVCOM [1:0] 2'h0 2'h1 2'h2 2'h3
Vcom Level modulation modulation VCOML VCOMH
TOSC - Sets for the oscillator test. TDFN - Sets for the function test.
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LGDP4531
Rev 1.15
Test Register 2 (RA1h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 IB8 IB7 0 IB6 0 IB5 IB4 IB3 0 IB2 0 IB1 IB0 G_TSD[1:0] TSHZ TSD_EN TSD[1:0]
TSD[1:0] - Sets TSD_EN - Sets
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TSHZ - Sets G_TSD - Sets
Test Register 3 (RA2h)
R/W RS W 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 T8CL 0 0 0 IB8 FRC IB7 0 IB6 0 IB5 0 IB4 0 IB3 0 IB2 IB1 IB0 HaltVreg MultiVci DLYEN
DLYEN - Used for Device Test. MultiVci - Used for Device Test. HaltVreg - Used for Device Test. FRC - Used for FRC mode test T8CL - Used for 8 color mode test
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LGDP4531
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Instruction List
Index Register 00h 01h 02h 03h 04h Start oscillation Driver output control 1 LCD Driving Control Entry mode Resizing Control Display Control 1 Display Control 2 Display Control 3 Display Control 4 External display Interface Control 1 Frame Marker Position External display Interface Control 2 Power Control 1 Power Control 2 Power Control 3 Power Control 4 Regulator Control IPS Control RAM Address Set (Horizontal Address) RAM Address Set (Vertical Address) RAM Data Gamma Control 1 Gamma Control 2 Gamma Control 3 Gamma Control 4 Gamma Control 5 Gamma Control 6 Gamma Control 7 Gamma Control 8 Gamma Control 9 Gamma Control 10 EPROM Control 1 EPROM Control 2 EPROM Control 3 Window Horizontal RAM Start Address Window Horizontal RAM End Address Window Vertical RAM Start Address Window Vertical RAM End Address
POR (0) VPP (0) PPROG (0) PKP1[2:0] (000) PKP3[2:0] (000) PKP5[2:0] (000) PRP1[2:0] (000) PKN1[2:0] (000) PKN3[2:0] (000) PKN5[2:0] (000) PRN1[2:0] (000) VRP1[4:0] VRN1[4:0] PWE (0) PA[1:0] (00) PDIN[6:0] (0000000) RA[1:0] (00) PDOUT[6:0] (0000000) HSA[7:0] (00000000) HEA[7:0] (11101111) VSA[8:0] (000000000) VEA[8:0] (100111111) VCMSEL[1:0] (00) WD[17:0] or RD[17:0] PKP0[2:0] (000) PKP2[2:0] (000) PKP4[2:0] (000) PRP0[2:0] (000) PKN0[2:0] (000) PKN2[2:0] (000) PKN4[2:0] (000) PRN0[2:0] (000) VRP0[3:0] VRN0[3:0] AD[7:0] (00000000) AD[16:8] (000000000) VCOMG (0) RSET[2:0] (000) VDV[4:0] (00000) RI[2:0] (000) RV[2:0] (011) SAP[2:0] (000) BT[3:0] (0000) DC1[2:0] (110) AP[2:0] (000) DC0[2:0] (110) PON (0) VCM[6:0] (0000000) RCONT (000) IPS (0) ENC[1:0] (000) RM (0) DM[1:0] (00) FMP[8:0] (000000000) VSPL (0) HSPL (0) DK (1) DSTB (0) EPL (0) SLP (0) VC[2:0] (000) VRH[3:0] (0000) DPL (0) PTDE[1:0] (00) FP[3:0] (1000) PTS[2:0] (000) PTG[1:0] (00) FMARKOE (0) SM (0) BC0 (0) TRI (0) DFM (0) BGR (0) RCV[1:0] (00) BASEE (0) SS (0) EOR (0) ORG (0) ID[1:0] (11) RCH[1:0] (00) GON (0) DTE (0) COL (0) BP[3:0] (1000) ISC[3:0] (0000) FMI[2:0] (000) RIM[1:0] (00) NW[5:0] (000000) AM (0) RSZ[1:0] (00) D[1:0] (00)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
Wave
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08h 09h 0Ah 0Ch 0Dh 0Fh 10h 11h 12h 13h 15h 16h 20h 21h 22h 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 40h 41h 42h 50h
51h 52h 53h
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LGDP4531
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60h 61h 6Ah 80h 81h 82h 83h
Driver Output Control 2 Base Image Display Control Vertical Scroll Control Partial Image 1 Display Position Partial Image 1 RAM Start Line Address Partial Image 1 RAM End Line Address Partial Image 2 Display Position Partial Image 2 RAM Start Line Address Partial Image 2 RAM End Line Address Panel Interface Control 1 Panel Interface Control 2 Panel Interface Control 3 Panel Interface Control 4 Panel Interface Control 5 Panel Interface Control 6 Test register 1 Test register 2 Test register 3
GS (0)
NL[5:0] (000000)
SCN[5:0] (000000) NDL (0) VL[8:0] (000000000) PTDP0[8:0] (000000000) PTSA0[8:0] (000000000) PTEA0[8:0] (000000000) PTDP1[8:0] (000000000) PTSA1[8:0] (000000000) PTEA1[8:0] (000000000) DIVI[1:0] (00) NOWI[2:0] (000) RTNI[4:0] (00000) EQI2[1:0] (00) EQI1[1:0] (00) MCPI[2:0] (000) DIVE[1:0] (00) RTNE[5:0] (000000) EQE2[1:0] (00) EQE1[1:0] (00) MCPE[2:0] (000) TDFN (0) G_TSD[1:0] (00) TSHZ (0) TOSC (0) TSD_EN (0) TVCOM[1:0] (00) TSD[1:0] (00) HaltVreg MultiVci DLYEN (0) (1) (0) VLE (0) REV (0)
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85h 90h 92h 93h 95h 97h 98h A0h A1h A2h
NOWE[3:0] (0000)
T8CL (0)
FRC (0)
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LGDP4531
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Reset Function
The LGDP4531 is initialized with a RESET input. During a reset period, the LGDP4531 is in a busy state and neither instruction nor access to the GRAM data from the MPU is accepted. The LGDP4531's internal power supply circuit unit is initialized also with a RESET input. The RESET period must be secured for at least 1ms. In case of power-on reset, wait until the RC oscillation frequency stabilizes (for 1 ms). During this period, neither access to the internal GRAM nor initial setting of instruction bits is accepted.
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Initial state of instruction bits (default) See the instruction list. The default value is shown in the parenthesis of each instruction bit cell. 2. RAM Data initialization The RAM data is not automatically initialized with a RESET input and must be initialized by software in a display-off period (D1-0 = "00"). 3. Output pin initial state *See note 1. LCD driver S1~S720 G1~G320 : VGL (= GND) 2. Vcom 3. VcomDC 4. VRS 5. VCS 6. VREG1OUT 7. VciOUT 8. VLOUT1 9. VLOUT2 10. VLOUT3 11. FMARK 12. Oscillator 13. SDO 4. Initial state of input/output pins*See note 1. C11+ 2. C113. C12+ 4. C125. C13+ 6. C137. C21+ 8. C219. C22+ 10. C2211. C23+ 12. C2313. VDD : GND : GND : GND : GND : GND : VGS : Hi-z : Vci : DDVDH ( = Vci) : GND : GND : Oscillate : GND : Hi-z : Hi-z : Hi-z : Hi-z : Vci1 : GND : DDVDH ( = Vci) : GND : DDVDH ( = Vci) : GND : DDVDH ( = Vci) : GND : VDD
Note: The above-mentioned initial states of output and input pins are the ones when the LGDP4531's power supply circuit is connected as exemplified in "Wiring example".
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5. Note on Reset function (1) When a RESET input is entered into the LGDP4531 while it is in deep standby mode, the LGDP4531 starts up the inside logic regulator and makes a transition to the initial state. During this period, the interface pins may be under an unstable condition. For this reason, do not enter a RESET input in deep standby mode. (2) When transferring instruction using either two or three transfer mode via 8-/9-/16-bit interface, make sure to execute a data transfer synchronization after executing a reset operation.
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Basic Mode operation of the LGDP4531
The basic operation modes of the LGDP4531 are shown in the following diagram. When making a transition from one mode to another, refer to instruction setting sequence.
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Figure 14
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Interface and data format
The LGDP4531 supports system interface for making instruction and other settings, and external display interface for displaying a moving picture. The LGDP4531 allows selecting an optimum interface according to the kind of display (moving or still picture) in order to transfer data efficiently. As external display interface, the LGDP4531 supports RGB interface and VSYNC interface, both enabling data rewrite operation without flickering the moving picture on display.
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RGB interface operation, the display operation is executed in synchronization with synchronous signals VSYNC, HSYNC, and DOTCLK. In synchronization with these signals, the LGDP4531 writes display data according to data enable signal (ENABLE) via RGB data signal bus (DB17-0). The display data is stored in the LGDP4531's GRAM in order to minimize the data transfer by transferring data only when it is necessary to switch the moving picture frames. The window address function specifies the RAM area where data is rewritten for moving picture display and enables displaying a moving picture and RAM data in other than the moving picture area simultaneously. In VSYNC interface operation, the internal display operation is synchronized with the frame synchronization signal (VSYNC). The VSYNC interface enables a moving picture display using system interface by writing data to the GRAM at more than a certain speed in synchronization with the falling edge of VSYNC. In this case, there are constraints in speed and methods of writing data to the internal RAM.
The LGDP4531 can operate in either one of the following four modes according to the state of display. The display operation mode is determined by setting the external interface control register. When switching between different modes, make sure to refer to mode switching sequence. Table 65 Operation Mode Internal clock operation (displaying still pictures) RGB interface (1) (displaying moving pictures) RGB interface (2) (rewriting still pictures while displaying moving pictures) VSYNC interface (displaying moving pictures)
RAM Access Setting (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0)
Display Operation Mode (DM) Internal clock operation (DM[1:0] = 00) RGB interface (DM[1:0] = 01) RGB interface (DM[1:0] = 01) VSYNC interface (DM[1:0] = 10)
Notes: 1. Instructions are set only via system interface. 2. The RGB and VSYNC interfaces cannot be used simultaneously. 3. Do not make changes to the RGB interface operation setting (RIM[1:0]) while RGB interface is in operation. 4. See the "External Display Interface" section for the mode transition sequence.
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CS * RS System Interface System Interface 18/16/9/8 RGB Interface 18/16/6 WR* (RD*) DB17-0
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ENABLE VSYNC RGB Interface HSYNC DOTCLK
Figure 15 LGDP4531's Interface
Internal clock operation The display operation is synchronized with signals generated from internal oscillator's clock (OSC) in this mode. Any input via external display interface is invalid in this operation. The internal RAM is accessible only via system interface. RGB interface operation (1) The display operation is synchronized with the frame synchronous signal (VSYNC), the line synchronous signal (HSYNC), and the dot clock signal (DOTCLK) in RGB interface operation. These signals must be supplied throughout the display period using RGB interface. The LGDP4531 transfers display data in units of pixels via DB17-0 pins. The display data is stored in the internal RAM. The combined use of high-speed RAM write mode and window address function enables the LGDP4531 to display a moving picture and the data in other than the moving picture RAM area simultaneously and transferring only data to be overwritten in the moving picture RAM area when7 rewriting the moving picture RAM area. This structure can minimize the total number of data transfer. The front porch (FP), back porch (BP), and the display (NL) periods are automatically calculated inside the LGDP4531 by counting the number of clocks of line synchronous signal (HSYNC) from the falling edge of the frame synchronous signal (VSYNC). Make sure to transfer pixel data via DB17-0 pins in accordance with these settings. RGB interface operation (2) This mode enables the LGDP4531 to rewrite RAM data via system interface while using RGB interface for display operation. To rewrite RAM data via system interface, make sure that display data is not transferred via RGB interface (ENABLE = high). To return to the RGB interface operation, change the ENABLE setting first and then set a new address and the index register to R22h. VSYNC interface operation The internal display operation is synchronized with the frame synchronous signal (VSYNC) in this mode. This mode enables the LGDP4531 to display a moving picture using system interface by writing data to the internal RAM at more than a minimum speed via system interface from the falling edge of frame synchronous (VSYNC). In this case, there are constraints in speed and methods of writing RAM data. For
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details, see the "VSYNC Interface" section. As an external input, only VSYNC signal input is valid in this mode. Any other input via external display interface is invalid. The front porch (FP), back porch (BP), and the display (NL) periods are automatically calculated from the frame synchronous signal (VSYNC) according to the register settings inside the LGDP4531.
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System Interface
The following are the kinds of system interfaces available with the LGDP4531. The interface operation is selected by setting the IM3/2/1/0 pins. The system interface is used for instruction setting and RAM access. Table 66 IM[3:0] 0000 www..com0001 0010 0011 010* 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Interface Mode with MPU Setting disabled Setting disabled 80-system 16-bit interface 80-system 8-bit interface Clock synchronous serial interface Setting disabled Setting disabled Setting disabled Setting disabled 80-system 18-bit interface 80-system 9-bit interface Setting disabled Setting disabled Setting disabled Setting disabled
DB pins DB17-10, DB8-1 DB17-10 SDI,SDO DB17-0 DB17-9 -
Colors 262,144 *see Note 1 262,144 *see Note 2 65,536 262,144 262,144 -
Notes: 1. 65,536 colors in 16-bit signal transfer mode. 2. 65,536 colors in 8-bit 2-transfer mode.
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80-system 18-bit Bus Interface
CSn* A1 HWR* (RD*) D[17:0] 18
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MPU
CS* LGDP4531 RS WR* (RD*) DB[17:0]
Figure 16 18-bit Interface
Instruction Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
RAM data write (1 transfer/pixel, 262k colors) Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GRAM write data
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 17 Data format for 18-bit interface
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80-system 16-bit Bus Interface
MPU CSn* A1 HWR* (RD*) D[15:0] 16 CS* LGDP4531 RS WR* (RD*) DB[17:10], DB[8:1]
Figure 18 16-bit Interface
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Instruction Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
RAM data write (1 transfer/pixel, 65k colors) - TRI = "0" GRAM data DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 DB DB DB DB DB DB DB DB 8 7 6 5 4 3 2 1
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RAM data write (2 transfers/pixel, 262k colors) - TRI = "1", DFM = "0" 1st transfer GRAM data 2nd transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RAM data write (2 transfers/pixel, 262k colors) - TRI = "1", DFM = "1" 1st transfer GRAM data 2nd transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 2 1 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 19 Data format for 16-bit interface
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Data Transfer Synchronous in 16-bit Bus Interface operation
The LGDP4531 supports a data transfer synchronization function to reset the counters for upper 16-/2-bit and lower 2-/16-bit transfers in 16-bit 2-transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 000H instruction is written four times consecutively to reset the upper and lower counters to restart data transfers from the upper 2/16 bits. By executing synchronization periodically, the system can recover from a runaway operation. Make sure to execute a transfer synchronization after a reset operation before transferring instruction.
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RS RD* WR* DB[17:10] DB[8:1] upper/ lower 000h 000h 000h 000h upper Synchronization
Figure 20 16-bit Data Transfer Synchronization
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80-system 9-bit Bus Interface
When transferring a 16-bit instruction, it is divided into the upper and lower 8 bits, and the upper 8 bits are transferred first (the LSB is not used). The RAM write data is also divided into the upper and lower 9 bits, and the upper 9 bits are transferred first. The unused DB pins must be fixed at either the IOVcc or IOGND level. When writing to the index register, the upper byte (8 bits) must be written.
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CSn* A1 HWR* (RD*) D[8:0] 9
CS* LGDP4531 RS WR* (RD*) DB[17:9]
Figure 21 9-bit Interface
Instruction Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
RAM data write (2 transfers/pixel, 262k colors) 1st transfer GRAM data 2nd transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 22 9-bit Interface Data Format
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Data Transfer Synchronous in 9-bit Bus Interface operation
The LGDP4531 supports a data transfer synchronization function to reset the counters for upper and lower 9-bit transfers in 9-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower counters to restart data transfers from the upper 9 bits. By executing synchronization periodically, the system can recover from a runaway operation. Make sure to execute a transfer synchronization after a reset operation before transferring instruction.
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RS RD* WR* DB[17:9] upper/ lower 000h 000h 000h 000h upper Synchronization
Figure 23 9-bit Data Transfer Synchronization
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80-system 8-bit Bus Interface
When transferring a 16-bit instruction, it is divided into the upper and lower 8 bits, and the upper 8 bits are transferred first. The RAM write data is also divided into the upper and lower 8 bits, and the upper 8 bits are transferred first. The RAM write data is expanded into 18 bits internally as shown below. The unused DB pins must be fixed at either the IOVcc or IOGND level. When writing the index register, the upper byte (8 bits) must be written.
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CSn* A1 HWR* (RD*) D[7:0] 8
CS* LGDP4531 RS WR* (RD*) DB[17:10]
Figure 24 8-bit Interface
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Instruction Input DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
RAM data write (2 transfers/pixel, 65k colors) - TRI = "0"
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GRAM data
1st transfer DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
2nd transfer DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RAM data write (3 transfers/pixel, 262k colors) - TRI = "1", DFM = "0" 1 transfer GRAM data
st
2 transfer
nd
3 transfer
rd
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RAM data write (3 transfers/pixel, 262k colors) - TRI = "1", DFM = "1" 1st transfer GRAM data 2nd transfer 3rd transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 25 8-bit Interface Data Format
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Data Transfer Synchronous in 8-bit Bus Interface operation
The LGDP4531 supports a data transfer synchronization function to reset the counters for upper and lower 8-bit transfers in 8-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower counters to restart data transfers from the upper 8 bits. By executing synchronization periodically, the system can recover from a runaway operation. Make sure to execute a transfer synchronization after a reset operation before transferring instruction.
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RS RD* WR* DB[17:10] upper/ lower 00h 00h 00h 00h upper Synchronization
Figure 26 8-bit Data Transfer Synchronization
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Serial Interface
The serial interface is selected by setting the IM3/2/1 pins to the IOGND/IOVcc/IOGND levels, respectively. The data is transferred via chip select line (CS), serial transfer clock line (SCL), serial data input line (SDI), and serial data output line (SDO). In serial interface operation, the IM0/ID pin functions as the ID pin, and the DB17-0 pins, not used in this mode, must be fixed at either IOVcc or GND level. The LGDP4531 recognizes the start of data transfer on the falling edge of CS input and starts transferring the start byte. It recognizes the end of data transfer on the rising edge of CS input. The LGDP4531 is selected when the 6-bit chip address in the start byte transferred from the transmission unit and the 6-bit device identification code assigned to the LGDP4531 are compared and both 6-bit data match, and then www..comthe LGDP4531 starts taking in data. The least significant bit of the device identification code is set with the ID pin. Send "01110" to the five upper bits of the device identification code. Two different chip addresses must be assigned to the LGDP4531 because the seventh bit of the start byte is assigned to the register select bit (RS). When RS = 0, an index register write operation is executed. When RS = 1, either an instruction write operation or a RAM read/write operation is executed. The eighth bit of the start byte is to select either read or write operation (R/W bit). The LGDP4531 receives data when the R/W = 0, and transfers data when the R/W = 1. When writing data to the GRAM via serial interface, the data is written to the GRAM after it is transferred in two bytes. The LGDP4531 writes data to the GRAM in units of 18 bits by adding the same bits as the MSBs to the LSB of R and B dot data. After receiving the start byte, the LGDP4531 starts transferring or receiving data in units of bytes. The LGDP4531 executes data transfer from the MSB. The LGDP4531's instruction takes 16-bit format and they are executed inside after it is transferred in two bytes (16 bits: DB15-0) from the MSB (The LGDP4531 expands RAM write data into 18-bit format when writing them to the internal GRAM). The first byte received by the LGDP4531 following the start byte is always the upper eight bits of instruction and the second byte is the lower 8 bits of instruction. In case of reading data from the GRAM, the LGDP4531 does not transfer valid data until first five bytes of data are read from the GRAM following the start byte. The LGDP4531 starts sending valid data as it reads the sixth and subsequent byte data. Table 67 Start byte format Transferred bits Start byte format 1 2 3 4 Device ID code 0 1 1 1 Note: ID bit is selected by setting the IM0/ID pin. Table 68 RS 0 0 1 1 R/W 0 1 0 1 Function Set an index register Read a status Write an instruction or RAM data Read an instruction or RAM data 5 0 6 ID 7 RS 8 R/W
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Instruction Input
1st transfer D15 D14 D13 D12 D11 D10 D9 D8
2nd transfer D7 D6 D5 D4 D3 D2 D1 D0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
RAM data write (2 transfers/pixel, 65k colors) - TRI = "0"
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GRAM data
1st transfer D15 D14 D13 D12 D11 D10 D9 D8
2nd transfer D7 D6 D5 D4 D3 D2 D1 D0
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RAM data write (3 transfers/pixel, 262k colors) - TRI = "1", DFM = "0" 1st transfer GRAM data 2nd transfer 3rd transfer
D23 D22 D21 D20 D19 D18 D15 D14 D13 D12 D11 D10 D7 D6 D5 D4 D3 D2
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 27 Data format for SPI
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Figure 28 Data Transfer in Serial interface
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VSYNC Interface
The LGDP4531 supports VSYNC interface, enabling the LGDP4531 to display a moving picture with minimum modifications to the existing system, using system interface and the frame synchronization signal (VSYNC).
MPU/ LCDC
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VSYNC LGDP4531 CS* RS WR* (RD*) DB[17:10] 18/16/9/8
Figure 29 VSYNC Interface The VSYNC interface is selected by setting DM[1:0] = 10 and RM = 0. In VSYNC interface operation, the internal display operation is synchronized with the VSYNC signal. By writing data to the internal RAM at a speed faster to a certain degree than the internal display operation speed, it becomes possible to rewrite data without flickering the moving picture on display and enables the LGDP4531 to display a moving picture using a system interface. The LGDP4531 performs the display operation with the internal clock signal generated from the internal oscillator and the VSYNC signal in this mode. In VSYNC mode, the data displayed on the screen are written to the internal RAM in order to transfer only the data to be written over the moving picture RAM area and thereby minimize the total data transfer required for moving picture display.
VSYNC
Write data to RAM through system interface
rewriting screen
rewriting screen
Display operation synchronized with internal clock
Figure 30 Moving Picture Data Transfers via VSYNC Interfce
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The VSYNC interface has the minimum speed of writing data to the internal RAM via the system interface and the minimum internal clock frequency, which are calculated from the following formulae. Internal clock frequency (fosc) [Hz] = FrameFrequency x (DisplayLines (NL) + FrontPorch (FP) + BackPorch (BP)) x 64 clocks x variance RAMWriteSpeed > 240 x DisplayLines (NL) (BackPorch (BP) + DisplayLines (NL) - margins) x 64 clocks x 1 fosc
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Note: When the RAM write operation does not start on the falling edge of VSYNC, the time from the edge of VSYNC until the start of RAM write operation must also be taken into account. An example of minimum RAM writing speed and internal clock frequency in VSYNC interface mode is as follows. [Example] Display size Lines Back/front porch Frame frequency 240 RGB x 320 lines 320 lines 14/2 lines (BP = 1110/FP = 0010) 60 Hz
Internal clock frequency (fosc) = 60 Hz x (320 + 2 + 14) lines x 64 Clocks x 1.1 / 0.9 = 1.6 MHz When setting the internal clock frequency, possible causes of variances must also be taken into consideration. In this example, the calculated internal clock frequency with the above register setting allows for a margin of 10% for variances and ensures to complete the display operation within one VSYNC cycle. In this example, variances attributed to the fabrication process of LSI and room temperature are counted in. Other possible causes of variances, such as differences in external resistors or voltage changes are not in consideration. It is necessary to allow for an enough margin if these factors must be incorporated. Minimum speed for RAM writing 240 x 320 / {((14 + 320 - 2) lines x 64 clock) / 1.6 MHz} = 5.7 MHz The above theoretical value is calculated on the premise that the LGDP4531 starts writing data to the internal RAM on the falling edge of VSYNC. There must at least be a margin of 2 lines between the physical display line where display operation is performed and the RAM line address where data write operation is performed. The RAM write speed of 5.7MHz or more on the falling edge of VSYNC will guarantee the completion of RAM write operation before the LGDP4531 starts displaying the RAM data on the screen, enabling rewriting the entire screen without flicker.
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Figure 31 Write/Display Operation Timing via VSYNC Interface
Notes in using the VSYNC interface
1. The above example of calculation gives a theoretical value. In the actual setting, other possible causes of variances not counted in the above example such as differences in internal oscillators should also be taken into consideration. It is strongly recommended to allow for an enough margin in setting a RAM writing speed. The above example of calculation gives a minimum value in case of rewriting the entire screen. If the moving picture display area is smaller than that, the range for setting a minimum RAM writing speed can have extra margins.
2.
Figure 32 RAM write margin
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3. 4.
After drawing 1 frame, a front porch period continues until the next input of VSYNC is detected. When switching from the internal clock operation mode (DM1-0 = "00") to the VSYNC interface mode, or the other way around, it is enabled from the next VSYNC cycle, i.e. after completing the display of the frame, which the LGDP4531 was internally processing when switching the modes. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode. In VSYNC interface mode, set the AM bit to "0" to transfer display data in the method mentioned above.
5. 6.
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Figure 33 Sequences to Switch between VSYNC and Internal Clock Operation Modes
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External Display Interface
The following RGB interfaces are available with the LGDP4531. The interface operation is set with the RIM[1:0] bits. The RGB interface is used for RAM access.
Table 69 RIM[1:0] 00 www..com 01 10 11 RGB Interface 18-bit RGB interface 16-bit RGB interface 6-bit RGB interface Setting disabled DB Pin DB[17:0] DB[17:10], DB[8:1] DB[17:12] -
RGB Interface
The display operation via RGB interface is synchronized with VSYNC, HSYNC, and DOTCLK. The RGB interface in combination with the window address function enables minimizing data transfer by rewriting data in high-speed with low power consumption only within the RAM area where data must be updated. In RGB interface operation, it is necessary to set back and front porch periods before and after the display period, respectively.
Figure 34 Display Operation via RGB Interface
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Polarities of VSYNC, HSYNC, ENABLE, and DOTCLK Signals
The polarities of VSYNC, HSYNC, ENABLE, and DOTCLK signals are changeable by setting the DPL, EPL, HSPL, and VSPL bits, respectively according to the system configuration.
RGB Interface Timing
The timing relationships of signals in RGB interface operation area as follows.
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16-18-bit RGB Interface Timing
Figure 35 Notes: 1. VLW HLW DTST : VSYNC Low period : HSYNC Low period : data transfer setup time
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6-bit RGB Interface Timing
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Figure 36 Notes: 1. VLW : VSYNC Low period HLW : HSYNC Low period DTST : Data transfer setup time 2. In 6-bit RGB interface operation, set the cycles of VSYNC, HSYNC, ENABLE, DOTCLK so that one pixel is transferred in units of three DOTCLKs via DB17-12 (DB5-0).
Moving Picture Display with the RGB Interface
The LGDP4531 supports RGB interfaces for displaying a moving picture and RAM for storing display data, which provides the following advantages in displaying a moving picture. 1. The window address function can minimize data transfer by specifying a moving picture RAM area 2. The high-speed write function enables RAM access in high speed with low power consumption 3. The data transfer is limited to a moving picture RAM area. 4. The reduction in data transfer contributes to the reduction in power consumption by the entire system 5. The combined use with system interface allows updating data in the still picture area, such as icons, while displaying a moving picture via RGB interface
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RAM access via system interface in RGB interface operation
The LGDP4531 allows RAM access via system interface in RGB interface operation. In RGB interface operation, data is written to the internal RAM in synchronization with DOTCLK while ENABLE is "Low". When writing data to the RAM via system interface, set ENABLE "High" to stop writing data via RGB interface. Then set RM = "0" to enable RAM access via system interface. When reverting to the RGB interface operation, wait for a time for a read/write bus cycle. Then, set RM = "1" and the index register to R22h to start accessing RAM via RGB interface. A conflict between RAM accesses via two different interfaces will not guarantee write operation. The following is an example of rewriting still picture data via system interface while displaying a moving www..compicture via RGB interface.
Figure 37 Updating the Still Picture Area while Displaying Moving Picture
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6-bit RGB Interface
The 6-bit RGB interface is selected by setting RIM[1:0] = 10. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 6-bit RGB data bus according to data enable signal (ENABLE). Unused pins DB[11:0] must be fixed at either IOVcc or IOGND level. The instructions are set only via system interface.
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LCDC
VSYNC HSYNC LGDP4531 DOTCLK ENABLE DB[17:12] 6
Figure 38 6-bit RGB interface
6-bit RGB interface (262k colors) 1st transfer GRAM data 2nd transfer 3rd transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 39 Data format for 6-bit interface
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Data Transfer Synchronization in 6-bit Bus Interface operation
The LGDP4531 has data transfer counters to count the first, second, and third 6-bit data transfers in 6-bit RBG interface operation. The transfer counters are always reset to the first data transfer on the falling edge of VSYNC. If there is a mismatch in the number of data transfers, the counters are reset to the first data transfer at the start of each frame (on the falling edge of VSYNC) and data transfer can be restarted in correct order from the next frame. In case of displaying a moving picture, which requires consecutive data transfer, this function can minimize the effect from the data transfer mismatch and help recover the display system to a normal state.
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Figure 40 6-bit Transfer Synchronization
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LGDP4531
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16-bit RGB Interface
The 16-bit RGB interface is selected by setting RIM1-0 = 01. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 16-bit RGB data bus according to data enable signal (ENABLE). The instructions are set only via system interface.
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LCDC
VSYNC HSYNC LGDP4531 DOTCLK ENABLE DB[17:13], DB[11:1] 16
Figure 41 16-bit RGB interface
16-bit RGB interface (65k colors) GRAM data DB DB DB DB DB 17 16 15 14 13 DB DB DB DB DB DB DB DB DB DB DB 11 10 9 8 7 6 5 4 3 2 1
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 42 Data format for 16-bit interface
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LGDP4531
Rev 1.15
18-bit RGB Interface
The 18-bit RGB interface is selected by setting RIM1-0 = 00. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. The display data is transferred to the internal RAM in synchronization with the display operation via 18-bit RGB data bus (DB17-0) according to data enable signal (ENABLE). The instructions are set only via system interface.
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LCDC
VSYNC HSYNC LGDP4531 DOTCLK ENABLE DB[17:0] 18
Figure 43 18-bit RGB interface
18-bit RGB interface (262k colors) GRAM data DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 44 Data format for 18-bit interface
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LGDP4531
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Notes on Using the External Display Interface
1. The following functions are not available in external display interface operation. Table 70 Functions Not Available in External Display Interface operation Fucntion External Display Interface Internal Display Interface Partial display Not available Available Scroll function Not available Available
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2. The VSYNC, HSYNC, and DOTCLK signals must be supplied throughout the display operation. 3. The reference clock for generating liquid crystal panel controlling signals in RGB interface operation is DOTCLK, not the internal clock generated from the internal oscillator. 4. In 6-bit RGB interface operation, 6-bit dot data (R, G, and B) is transferred in synchronization with DOTCLK. In other words, it takes three DOTCLKs to transfer one pixel. 5. In 6-bit RGB interface operation, each 6-bit dot data (R, G, and B) is transferred in synchronization with DOTCLK. Take this into consideration and make sure to set the cycles of VSYNC, HSYNC, DOTCLK, ENABLE, and data transfer via DB17-12 so that data transfer is completed in units of pixels. 6. When switching between the internal operation mode and the external display interface operation, follow the sequences in Figure 43 RGB and Internal Clock Operation Mode switching sequences. 7. In RGB interface operation, a front porch period continues until the next VSYNC input is detected after the end of each frame period. 8. In RGB interface operation, use high-speed write function (HWM = 1) when writing data to the internal RAM.
9. In RGB interface operation, RAM address AD16-0 is set in the address counter every frame on the falling edge of VSYNC.
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LGDP4531
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Figure 45 RGB and Internal Clock Operation Mode switching sequences
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LGDP4531
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RAM Address and Display Position on the Panel
The LGDP4531 has memory to store display data of 240RGB x 320 lines. The LGDP4531 incorporates a circuit to control partial display, which enables switching driving methods for full-screen display and partial display. The LGDP4531 allows separate settings for display control and driving position control and specifying a RAM area for each image displayed on the screen. This structure enables designing a display on the screen not constrained by the mounting position of the display panel.
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The following is the sequence of settings for full-screen and partial display. 1. Set (PTSAx, PTEAx) to specify the RAM area for each partial image 2. Set the display position of each partial image on the base image with PTDPx. 3. Set NL to specify the number of lines to drive the liquid crystal panel to display the base image 4. After display ON, set display enable bits (BASEE, PTDE0/1) to display respective images In driving the liquid crystal panel, the clock signal for gate line scan is supplied consecutively via interface in accordance with the number of lines to drive the liquid crystal panel (NL setting). When switching the display position in horizontal direction, the register setting in SS bit is required when writing RAM data. Table 71 Base image Display ENABLE BASEE Numbers of Lines NL RAM area (BSA, BEA) = (9'h000, 9'h13F)
Notes : 1: The base image is displayed from the first line of the screen. 2: Make sure NL 320 (lines) = BEA - BSA when setting a base image RAM area. BSA and BEA are fixed to 9'h000, 9'h13F, respectively. Table 72 Partial image 1 Partial image 2 Display ENABLE PTDE0 PTDE1 Display position (PTDP0, PTEA0) (PTDP1, PTEA1) RAM start position PTSA0 PTSA1
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Figure 46 RAM Address, display position and drive position
Restrictions in setting display control instruction
The following are the constraints in setting coordinates of display data, display position, and partial image display.
Screen setting
In setting the number of lines to drive the liquid crystal panel, make sure that the total number of lines is within the limit: NL 320 lines Base image display 1. The base image is displayed from the first line of the screen: BSA = 1st line (of the display panel) 2. The base image RAM area specified with BSA, BEA must include the same or more number of lines necessary to drive the liquid crystal panel (NL setting): BEA - BSA NL Partial image display Set the partial image RAM area setting registers (PTSAx, PTEAx bits) and the partial position setting registers (PTDPx bits) so that the RAM areas and the display positions of partials do not overlap each other. 0 PTDP0 PTEA0 < PTDP1 PTEA1 NL
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LGDP4531
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The following figure shows the relationship among the RAM address, display position, and driving positions of the panel.
Display Data output order LCD panel Physical line address
RAM line address
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1 2 3 4 5 6 : : : : : : : :
0 (1st line) 1 (2nd line) 2 (3rd line)
BSA0 = 9'h000
PTDP0
PTSD image 1 Display area
NL (n lines) PTEA0 PTDP1
PTSD image 2 Display area
PTEA1
n-1
BEA0 PTSA0 PTSA0+(PTEA0-PTDP0) PTSA1 PTSA1+(PTEA1-PTDP1)
BEA = 9'h13F
Figure 47 Display RAM Address and display position Note: In this figure, the RAM address is defined in relation to the display position on the panel. Inside the LGDP4531, the RAM address area where the data is written is defined within a window address area on the GRAM address mapping.
Instruction setting example
The followings are the examples of settings for 240(RGB) x 320(lines) panels. 1. Full screen display (no partial) The following is an example of setting for full screen display. Table 73 Base image display insruction BASEE 1 NL[5:0] 6'h27 PTDE0 PTDE1 0 0
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LGDP4531
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Display Data output order
LCD panel Physical line address
RAM line address
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1 2 3 4 5 6 : : : : : : : :
0 (1st line) 1 (2nd line) 2 (3rd line)
BSA = 9'h000
NL (320)
Base image
BASE image RAM area
320
319 (320th line)
BEA = 9'h13F
Figure 48 Full screen display (no partial) 2. Partial only The following is an example of setting for displaying partial image 1 only and turning off the base image display. The partial image 1 is displayed at the position designated by users. Table 74 Base image display insruction BASEE 0 NL[5:0] 6'h27 Partial image 1 display insruction PTDE0 1 PTSA0[8:0] 9'h000 PTEA0[8:0] 9'h08F PTDP0[8:0] 9'h080 Partial image 2 display insruction PTDE1 0 PTSA1[8:0] 9'h000 PTEA1[8:0] 9'h000 PTDP1[8:0] 9'h000
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Display Data output order
LCD panel Physical line address
RAM line address
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1 2 3 4 5 6 : : : : : : : :
0 (1st line) 1 (2nd line) 2 (3rd line)
PTSA0 = 9h000
Partial image 1 RAM area
PTSA0+(PTEA0-PTDP0)
PTDP0 (8'h80)
NL (320)
Partial image Display area PTEA0 (8'h8F) Base image (non-lit display) BASE image RAM area
320
319 (320th line)
BEA = 9'h13F
Figure 49 Partial display
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LGDP4531
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Resizing function
The LGDP4531 supports resizing function (x 1/2, x 1/4), which is executed when writing image data. The resizing function is enabled by setting a window address area and the RSZ bit representing the contraction factor (x1/2 or x1/4) of the image. This function enables the LGDP4531 to write the resized image data directly to the internal RAM, while allowing the system to transfer the original-sized image data. The resizing function allows the system just to transfer data as usual even when resizing of the image is required. This feature makes a resized image easily available with various applications such as camera display, sub panel display, thumbnail display and so on.
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The LGDP4531 processes the contraction of an image simply by selecting pixels. For this reason, the resized image may appear distorted when compared with the original image. Check the resized image before use.
Figure 50 Data transfer in resizing
Table 75 Origianl image size (X x Y ) 640x480(VGA) 352x288(CIF) 320x240(QVGA) 176x144(QCIF) 120x160 132x176
Resized image Size 1/2 (RSZ = 2'h1) 1/4 (RSZ = 2'h3) 320x240 160x120 176x144 88x72 160x120 80x60 88x72 44x36 60x80 30x40 66x88 33x44
Resizing setting
The RSZ bit sets the resizing (contraction) factor of an image. When setting the RAM area using the window address function, the window address area must be just the size of the resized picture. If resizing creates surplus pixels, which are calculated from the following equations, set them with the RCV, RCH bits before writing data to the internal RAM.
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Figure 51 Resizing Setting, surplus pixel calculation Table 76 Image (before resizing) Number of data in horizontal direction Numbef of data in vertical direction Resizing ratio Resizing setting in the LGDP4531 Resizing setting Numbef of data in horizontal direction Numbef of data in vertical direction RAM writing start address RAM window address
X Y 1/N
RSZ RCH RCV AD HAS HEA VSA VEA
N-1 L M (X0,Y0) X0 X0+Rx-1 Y0 Y0+Ry-1
Notes to Resizing function
1. Set the resizing instruction bits (RSZ, RCV, and RCH) before writing data to the internal RAM. 2. When writing data to the internal RAM using resizing function, make sure to start writing data from the first address of the window address area in units of lines. 3. Set the window address area in the internal RAM to fit the size of the resized image. 4. Set AD16-0 before start transferring and writing data to the internal RAM. 5. Set the RCH, RCV bits only when using resizing function and there are remainder pixels. Otherwise (if RSZ = 2'h0), set RCH = RCV = 2'h0.
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LGDP4531
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Figure 52 RAM write operation sequence in resizing
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LGDP4531
Rev 1.15
FMARK function
The LGDP4531 outputs an FMARK pulse in the timing when driving the line specified with FMP[8:0] bits. The FMARK signal can be used as a trigger signal in writing display data in synchronization with display operation by detecting the address where the RAM data is read out for display operation. The output interval of FMARK pulse can be set with the FMI[2:0] bits. Set the FMI[2:0] bits in accordance with display data rewrite cycle and data transfer rate. Sets FMARKOE = 1 when outputting FMARK pulse from the FMARK pin.
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Table 77 FMP[8:0] 9'h000 9'h001 9'h002 : 9'h14D 9'h14E 9'h14F 9'h150 ~ 1FF
FMARK output position 0 1 2 : 333 334 335 Setting disabled
Table 78 FMI[2:0] 3'h0 3'h1 3'h3 3'h5 Other setting
FMARK output interval One frame period 2 frame periods 4 frame periods 6 frame periods Setting disabled
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LGDP4531
Rev 1.15
FMP setting example
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Figure 53
Display operation synchronous data transfer using FMARK
The LGDP4531 uses FMARK signal as a trigger signal to start writing data to the internal GRAM in synchronization with display scan operation.
Figure 54 Display synchronous data transfer interface The LGDP4531 writes display data to the internal GRAM at a speed faster to a certain degree than that of display operation in order to enable a moving picture display via the system interface without flicker. By writing all display data to the internal RAM, only the data tp be overwritten in the moving picture RAM area is transferred and the total data transfer for moving picture display can be minimized.
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LGDP4531
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Figure 55 Moving Picture Data Transfers via FMARK function
The data transfer operation via FMARK function has a minimum RAM data rite speed an internal clock frequency, which must be more than the theoretical values chlculated from the following equations Internal clock frequency (fosc) [Hz] = FrameFrequency x (DisplayLines(NL) + FrontPorch(FP) + BackPorch(BP)) x 64(clocks) x variance RAMWriteSpeed > 240 x DisplayLines (NL) (BackPorch (BP) + DisplayLines (NL) - margins) x 64 clocks x 1 fosc
Note : When RAM write operation is not started right after the rising edge of FMARK, the time from the rising edge of FMARK until the start of RAM write operation must also be taken into account.
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LGDP4531
Rev 1.15
Window Address Function
The window address function enables writing display data consecutively in a rectangular area (a window address area) made on the internal RAM. The window address area is made by setting the horizontal address register (start: HSA7-0, end: HEA 7-0 bits) and the vertical address register (start: VSA8-0, end: VEA8-0 bits). The AM and I/D bits set the transition direction of the RAM address (either increment or decrement, horizontal or vertical, respectively). Setting these bits enables the LGDP4531 to write data including image data consecutively without taking data wrap position into account.
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window address area must be made within the GRAM address map area. Also, the AD16-0 bits (RAM address set register) must be set to an address within the window address area. [Window address area setting range] (Horizontal direction) (Vertical direction) [RAM Address setting range] (RAM address) 8'h00 HSA HEA 8'hEF 9'h000 VSA VEA 9'h13F HSA AD7-0 HEA VSA AD16-8 VEA GRAM address MAP
17'h00000 17'h000EF
Window address area
17'h02010 17'h02110 17'h0202F 17'h02012F
17'h05F10
17'h05F2F
17'h13F00 Window address area specification HSA = 8'h10, HEA = 8'h2F I/D = 2'h3 (increment) VSA = 9'h020, VEA = 9'h05F AM = 1'h0 (Horizontal write) ORG = 0 RAM address set = 17'h02010 (Arbitray) ORG = 1 RAM address set = 17'h00000
17'13FEF
Figure 56 Automatic address update within a Window Address Area
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LGDP4531
Rev 1.15
EPROM Control
LGDP4531 has an embedded EPROM which is a 32-bit one-time programmable (OTP) IP from eMemory Technology Inc. (EO01X32GCV1). EO01X32GCV1 is a CMOS, 1bit (1-bit) program OTP logic device. The main memory block is organized as 8-bits by 4 banks. See the data sheet of EO01X32GCV1. The pins of the embedded EPROM can be controlled using the EPROM control 1 (R60h) register as shown below. Table 79
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POR = 0V/1.8V VPP = 1.8V/7.2V PPROG = 0V/1.8V PWE = 0V/1.8V PA[1:0] = 0V/1.8V PDIN[6:0] = 0V/1.8V
Bit fields of register R40h POR = 0/1 VPP = 0/1 PPROG = 0/1 PWE = 0/1 PA[1:0] = 0/1 PDIN[6:0] = 0/1
The RA[1:0] of register R61h selects one of four EPROM bytes.
Accessing EPROM control registers, follow the timing requirements of read and program cycles.
Read Cycle
Tvd s 1.8v Tvd r 0v 1.8v
VDD
0v
VPP
0v
Trst Tpor
0v
POR
Taa
PDOB[31:0]
XXX
Data out
XXX
Program Cycle
Tvds 1.8v Tvps 7.2v Tpps 1.8v 1.8v Tppr 0v Tvdr
VDD
0v
0v
VPP
0v
PPROG
Tpw Tvph
PWE
Tas Tah Valid Addr. Tds Tdh Valid Data Valid Data XXX Valid Addr. Tvr Next operation XXX
PA[1:0]
XXX
PDIN[6: 0]
XXX
Figure 57 EPROM timings
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LGDP4531
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Table 80 Parameter Risimg Time / Fallimg Time Data Access Time Power-on Pulse Width Time Address / Data Setup Time Address / Data Hold Time External VPP Setup Time www..com External VPP Hold Time Program Recovery Time Program Pulse Width VDD Setup Time VDD Recovery Time PPROG Setup Time PPROG Recovery Time Symbol Tr / Tf Taa Tpor Tas / Tds Tah / Tdh Tvps Tvph Tvr Tpw Tvds Tvdr Tpps Tppr EO01X32GCV1 Min Max 1 70 70 4 9 0 0 10 90 110 0 0 10 10 Unit ns ns ns ns ns ns ns us us ms ms ns ns
Notes 1. All electrical and timing parameters listed above are based on SPICE (or equivalent) simulations and subject to changes after silicon verification. 2. All program signals that align together in the timing diagrams should be derived from the rising clock edge. 3. All timing measurements are from the 50% of the input to 50% of the output. 4. All input waveforms have rising time (tr) and falling time (tf) of 1ns from 10% to 90% of the input waveforms. 5. For capacitive loads greater than 1pF, access time will increase by 1ns per pF of additional loading. 6. Program time means one byte program time in user mode
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LGDP4531
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Scan Mode Setting
The LGDP4531 allows for changing the gate-line/gate driver assignment and the shift direction of gate line scan in the following 4 different ways by combination of SM and GS bit settings. These combinations allow various connections between the LGDP4531 and the LCD panel.
SM 0 GS 0 Scan direction
Odd-numbered lines
G1
G2
Even-numbered lines
G1, G2, G3, G4, ..., G318, G319, G320
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TFT panel
G319 G1 G319
G320 G320 G2
LGDP4531 0 1
Odd-numbered lines
G1
G2
Even-numbered lines
G320, G319, G318, ..., G4, G3, G2, G1
TFT panel
G319 G1 G319
G320 G320 G2
LGDP4531 1 0 G1 TFT panel G1, G3, G5, ..., G317, G319, G2, G4, G6, ..., G318, G320
G319
G2
G320 G1 G319 LGDP4531 1 1 G1 TFT panel G320, G318, G316, ..., G6, G4, G2, G319, G317, G315, ..., G5, G3, G1 G320 G2
G319
G2
G320 G1 G319 LGDP4531 G320 G2
Figure 58
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LGDP4531
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8-color Display Mode
The LGDP4531 has a function to display in eight colors, where the available grayscales are only V0 and V63, and the power supplies for other grayscales (V1 to V62) are cut off to reduce power consumption. In 8-color display mode, the -adjustment registers P0KP0-P0KP5, P0KN0-P0KN5, P0RP0, P0RP1, P0RN0, P0RN1, P0FP0-P0FP3, and P0FN0-P0FN3, are disabled and the power supplies for V1 to V62 are halted. The LGDP4531 does not require rewriting GRAM data by writing the MSB of each dot data to the rest to display in 8 colors.
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Figure 59 8-color Display mode
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LGDP4531
Rev 1.15
Line Inversion AC Drive
The LGDP4531, in addition to the frame-inversion liquid crystal AC drive, supports the n-line inversion AC drive, in which the polarity of liquid crystal is inverted in units of n lines, where n takes a number from 1 to 64. The quality of display will be improved by using n-line inversion AC drive. In determining n (the value set with the NW bits +1), which represents the number of lines that determines the timing of liquid crystal polarity inversion, check the quality of display on the liquid crystal panel in use. Note that setting a smaller number of lines will raise the frequency of liquid crystal polarity inversion and increase charging/discharging current on liquid crystal cells .
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One frame Back porch 12 Frame-inversion AC drive - 320 line drive 3 4 321 322 Front porch Back porch 336 12 3 4 321 322 One frame Front porch 336
Line-inversion AC drive - 320 line drive
Figure 60 Example of Alternating Signals for n-line Inversion
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LGDP4531
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Frame-Frequency Adjustment Function
The LGDP4531 supports a function to adjust frame frequency. The frame frequency for driving the LCD can be adjusted by setting the DIVI/E, RTNI/E bits without changing the oscillation frequency. To switch frame frequencies according to whether displaying a moving picture or displaying a still picture, set a high oscillation frequency in advance. Then, set a low frame frequency to save power consumption when displaying a still picture. When displaying a moving picture, set the frequency high.
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Relationship between the liquid crystal Drive Duty and the Frame Frequency
The relationship between the liquid crystal drive duty and the frqme frequency is calaulated from the following equation. The frame frequency can be adjusted by setting the 1H period adjustment (RTNI/E) bit and the operation clock division (DIVI/E) bit. Equlation for calculating frame frequency Frame Frequency = Fosc Number Of Clocks Per Line x Division Ratio x (Line + FP + BP)
Fosc : RC oscillation frequency Number of Clocks per line : RTNI/E bit Division Ratio : DIVI/E bit Line : number of lines to drive the LCD (NL bit) FP : Number of lines for front porch BP : Number of lines for back porch Example of Calculation : when maximum frame frequency = 60Hz Number of lines : 320 lines 1H period : 64 Clock cycles (RTNI/E[4:0] = "10000") Division ratio of operating clock : 1/1 Front porch : 2 lines Back porch : 14 lines Fosc = 60 (Hz) x 64 (clocks) x 1/1 x (320 + 2 + 14) (Lines) = 1. 29(MHz) In this case, the RC oscillation frequency is to set to 1.29MHz. Adjust the value of the external resistor coneected to the RC oscillator so that RC oscillation frequency becomes 1.29MHz.
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LGDP4531
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Partial Display Function
The partial display function allows the LGDP4531 to drive linies selectively to display partial images by setting partial display control registers. The lines not used for displaying partial images are driven with non-display level to reduce power consumption. The power saving effect can be enhanced in combination with 8-color display mode. Check the display quality when using low power consumption functions.
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G1 G7
st
1
Screen: 7 lines
Non-display area
G26 G42
OCT 14th 10:18am
2 Screen: 17 lines
nd
Non-display area
The number of lines to drive LCD panel: NL = 27h (320 raster-rows) st 1 screen setting : PTDP0 = 00h, PTSA0 = 00h, PTEA0 = 06h nd 2 screen setting : PTDP1 = 19h, PTSA1 = 19h, PTEA1 = 29h, PTDE = 03h
Figure 61
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LGDP4531
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Liquid crystal panel interface timing
The relationships between RGB interface signals and liquid crustal panel control signals in interhal operation and RGB interface operations are as follows.
Internal clock operation
One Frame
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Reference point
Reference point
Reference point
Reference point
Reference point
Reference point
Reference point
Reference point
Reference point
FMARK (FMP = BP - 1) NOWI G1
G2
G320 S(3n+1) S(3n+2) S(3n+3) n = 0 ~ 239 VCOM MCPI
Figure 62
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LGDP4531
Rev 1.15
RGB Interface operation
VSYNC
HSYNC
DOTCLK
ENABLE
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DB
1
2
3
4
5
6
318
319
320
1
2
FMARK
G1
G2
G320
S(3n+1) S(3n+2) S(3n+3) n = 0 ~ 239 VCOM
Figure 63
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LGDP4531
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Oscillator
The LGDP4531 generates oscillation with the LGDP4531's internal RC oscillators by placing an external oscillation resistor between the OSC1 and OSC2 pins. The oscillation frequency varies due to resistance value of external resistor, wiring distance, and operating supply voltage. For example, placing an Rf resistor of a larger resistance value, or lowering the supply voltage level brings down the oscillation frequency. See the "Notes to Electrical Characteristics" section for the relationship between resistance value of Rf resistor and oscillation frequency.
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LGDP4531 OSC1 Rf OSC2 Note 1) Place a Rf resistor as close to OSC1 and OSC2 pins as possible.
LGDP4531 OSC1 Rf OSC2 Note 2) Make sure not to arrange other wiring beneath or close to the OSC1 and OSC2 wiring to prevent coupling.
Figure 64
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LGDP4531
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-Correction Function
The LGDP4531 has the -correction function to display in 262,144 colors simultaneously. The correction is performed with 3 groups of registers determining eight reference grayscale levels, which are gradient adjustment, amplitude adjustment and fine-adjustment registers. Each register groups further consists of register groups of positive and negative polarities. Each register group is set independently to other register groups, making the LGDP4531 available with liquid crystal panels of various characteristics.
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Graphics RAM (GRAM)
Display data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Positive Polarity Register
VRP03 VRP14 VRP13
PKP02 PKP12 PKP22 PKP32 PKP42 PKP52 PRP02 PRP12 VRP02 VRP12
PKP01 PKP11 PKP21 PKP31 PKP41 PKP51 PRP01 PRP11 VRP01 VRP11
PKP00 PKP10 PKP20 PKP30 PKP40 PKP50 PRP00 PRP10 VRP00 VRP10 8 64
6 6
6
V0 64- level grayscale Control 64- level grayscale Control 64- level grayscale Control
V1
PKN32 PKN42 PKN52 PRN02 PRN12 VRN03 VRN02 VRN14 VRN13 VRN12
Negative Polarity Register
PKN02 PKN01 PKN00 PKN12 PKN11 PKN10 PKN22 PKN21 PKN20 PKN31 PKN41 PKN51 PRN01 PRN11 VRN01 VRN11 PKN30 PKN40 PKN50 PRN00 PRN10 VRN00 VRN10
LCD driver
V63
LCD driver
LCD driver
R
G LCD
B
Figure 65 Grayscale control
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LGDP4531
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Grayscale Amplifier Unit Configuration
The following figure illustrates the grayscale amplifier unit of the LGDP4531. To generate 64 grayscale voltages (V0 to V63), the LGDP4531 first generates eight reference grayscale voltages (VINP0-7/VINN0-7). The grayscale amplifier unit then divides eight reference grayscale voltages with the ladder resistors incorporated therein.
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Figure 66 Grayscale amplifier unit
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LGDP4531
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VxRN0[3:0] PxRN0[2:0] PxRN1[2:0] VxRN1[4:0]
VREG1OUT VRP0 0-15R
VDD DDVDH
VRN0 0-15R 5R
VDD DDVDH
5R
4R*7
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VRHP 0-28R
8to1 SEL
4R*7
8to1 SEL
VDD DDVDH
VRHN 0-28R
1R*7
8to1 SEL
1R*7
8to1 SEL
5R
VDD DDVDH
5R
VDD DDVDH
1R*7
8to1 SEL
1R*7
8to1 SEL
16R
VDD DDVDH
16R
VDD DDVDH
1R*7
8to1 SEL
1R*7
8to1 SEL
5R
VDD DDVDH
5R
VDD DDVDH
1R*7
8to1 SEL
VDD DDVDH
1R*7
8to1 SEL
VDD DDVDH
VRLP 0-28R
VRLN 0-28R
4R*7
8to1 SEL
4R*7
8to1 SEL
5R VRP1 0-31R 8R VGS
5R VRN1 0-31R 8R
Figure 67 Ladder resistor units and 8-to-1 selectors (IPS=0)
VDD DDVDH
PxKN0[2:0] PxKN1[2:0] PxKN2[2:0] PxKN3[2:0] PxKN4[2:0] PxKN5[2:0]
VxRP0[3:0] PxRP0[2:0] PxRP1[2:0] VxRP1[4:0]
PxKP0[2:0] PxKP1[2:0] PxKP2[2:0] PxKP3[2:0] PxKP4[2:0] PxKP5[2:0]
127
LGDP4531
Rev 1.15
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Figure 68 Ladder resistor units and 8-to-1 selectors (IPS=1)
128
LGDP4531
Rev 1.15
-Correction Register
The -correction registers of the LGDP4531 consist of gradient adjustment, amplitude adjustment, and fine adjustment registers, each of which has registers of positive and negative polarities. Each different register group can be set independently to others, enabling adjustment of grayscale voltage levels in relation to grayscales set optimally for -characteristics of a liquid crystal panel. These -correction register settings and the reference levels of the 64 grayscales to which the three kinds of adjustments are made (bold lines in the following figure) are common to all RGB dots.
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Gradient adjustment
1. Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient of the curve representing the relationship between the grayscale and the grayscale voltage level around middle grayscales without changing the dynamic range. To adjust the gradient, the resistance values of grayscale reference voltage generating variable resistors (VRHP(N)/VRLP(N)) in the middle of the ladder resistor unit are adjusted. The registers consist of positive and negative polarity registers, allowing asymmetric drive. 2. Amplitude adjustment registers The amplitude adjustment registers are used to adjust the amplitude of grayscale voltages. To adjust the amplitude, the resistance values of the grayscale voltage generating variable resistors (VRP(N)1/0) at the top and bottom of the ladder resistor unit are adjusted. Same with the gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers. 3. Fine adjustment registers The fine adjustment registers are used to fine-adjust grayscale voltage levels. To fine-adjust grayscale voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register generated from the ladder resistor unit, in respective 8-to-1 selectors. Same with other registers, the fine adjustment registers consist of positive and negative polarity registers.
G r a y S c a l e V o lt a g e Gray Scale Number
Amplitude adjustment
G r a y S c a l e V o lt a g e Gray Scale Number
G r a y S c a l e V o lt a g e Gray Scale Number
Fine adjustment
Figure 69
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LGDP4531
Rev 1.15
Table 81 List of registers
Register Groups Gradient adjustment Amplitude adjustment Fine adjustment Positive Polarity PRP0[2:0] PRP1[2:0] VRP0[3:0] VRP1[4:0] PKP0[2:0] PKP1[2:0] PKP2[2:0] PKP3[2:0] PKP4[2:0] PKP5[2:0] Negative Polarity PRN0[2:0] PRN1[2:0] VRN0[3:0] VRN1[4:0] PKN0[2:0] PKN1[2:0] PKN2[2:0] PKN3[2:0] PKN4[2:0] PKN5[2:0] Description Variable resistor VRHP(N) Variable resistor VRHP(N) Variable resistor VRP(N)0 Variable resistor VRP(N)1 8-to-1 selector ( voltage level of grayscale 1) 8-to-1 selector ( voltage level of grayscale 8) 8-to-1 selector ( voltage level of grayscale 20) 8-to-1 selector ( voltage level of grayscale 43) 8-to-1 selector ( voltage level of grayscale 53) 8-to-1 selector ( voltage level of grayscale 62)
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Ladder Resistors and 8-to-1 Selector
Block Configuration
The reference voltage generating unit as illustrated in page 3-4 consists of two ladder resistor units including variable resistors and 8-to-1 selectors. Each 8-to-1 selector selects one of the 8 voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage. Both variable resistors and 8-to-1 selectors are controlled according to the correction registers. This unit has pins to connect a volume resistor externally to compensate differences in various characteristics of panels.
Variable Resistors
The LGDP4531 uses variable resistors of the following three purposes: gradient adjustment (VRHP(N)/VRLP(N)) and amplitude adjustment (VRP(N)0~1). The resistance values of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as follows. Table 82 Gradient adjustment Register Resistance PRP(N)0/1[2:0] VRHP(N) VRLP(N) 3'h0 0R 3'h1 4R 3'h2 8R 3'h3 12R 3'h4 16R 3'h5 20R 3'h6 24R 3'h7 28R Table 83 Amplitude adjustment(1) Register Resistance VRP(N)0[3:0] VRP(N)0 4'h0 4'h1 4'h2 : 4'h12 4'h13 4'h14 4'h15 0R 1R 2R : 12R 13R 14R 15R Table 84 Amplitude adjustment(2) Register Resistance VRP(N)1[4:0] VRP(N)1 5'h0 5'h1 5'h2 : 5'h28 5'h29 5'h30 5'h31 0R 1R 2R : 28R 29R 30R 31R
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LGDP4531
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8-to-1 Selectors
The 8-to-1 selector selects one of eight voltage levels generated from the ladder resistor unit according to the fine adjustment register, and output the selected voltage level as a reference grayscale voltage (VINP(N)1~ VINP(N 6). The table below shows the setting in the fine adjustment register and the selected voltage levels for respective reference grayscale voltages Table 85 Fine adjustment registers and selected voltage
PKP(N)[2:0] 3'h0 www..com 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 Selected Voltage VINP(N)1 VINP(N)2 KVP(N)1 KVP(N)9 KVP(N)2 KVP(N)10 KVP(N)3 KVP(N)11 KVP(N)4 KVP(N)12 KVP(N)5 KVP(N)13 KVP(N)6 KVP(N)14 KVP(N)7 KVP(N)15 KVP(N)8 KVP(N)16 VINP(N3 KVP(N)17 KVP(N)18 KVP(N)19 KVP(N)20 KVP(N)21 KVP(N)22 KVP(N)23 KVP(N)24 VINP(N)4 KVP(N)25 KVP(N)26 KVP(N)27 KVP(N)28 KVP(N)29 KVP(N)30 KVP(N)31 KVP(N)32 VINP(N)5 KVP(N)33 KVP(N)34 KVP(N)35 KVP(N)36 KVP(N)37 KVP(N)38 KVP(N)39 KVP(N)40 VINP(N)6 KVP(N)41 KVP(N)42 KVP(N)43 KVP(N)44 KVP(N)45 KVP(N)46 KVP(N)47 KVP(N)48
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LGDP4531
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The grayscale voltage levels for V0~V63 grayscales are calculated from the following formula. Table 86 Formula for calculating voltage (IPS=0)
Pin KVP0 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 www..comKVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP49 Formula VREG1OUT - V*VRP0/SUMRP VREG1OUT - V*(VRP0+5R)/SUMRP VREG1OUT - V*(VRP0+9R)/SUMRP VREG1OUT - V*(VRP0+13R)/SUMRP VREG1OUT - V*(VRP0+17R)/SUMRP VREG1OUT - V*(VRP0+21R)/SUMRP VREG1OUT - V*(VRP0+25R)/SUMRP VREG1OUT - V*(VRP0+29R)/SUMRP VREG1OUT - V*(VRP0+33R)/SUMRP VREG1OUT - V*(VRP0+33R+VRHP)/SUMRP VREG1OUT - V*(VRP0+34R+VRHP)/SUMRP VREG1OUT - V*(VRP0+35R+VRHP)/SUMRP VREG1OUT - V*(VRP0+36R+VRHP)/SUMRP VREG1OUT - V*(VRP0+37R+VRHP)/SUMRP VREG1OUT - V*(VRP0+38R+VRHP)/SUMRP VREG1OUT - V*(VRP0+39R+VRHP)/SUMRP VREG1OUT - V*(VRP0+40R+VRHP)/SUMRP VREG1OUT - V*(VRP0+45R+VRHP)/SUMRP VREG1OUT - V*(VRP0+46R+VRHP)/SUMRP VREG1OUT - V*(VRP0+47R+VRHP)/SUMRP VREG1OUT - V*(VRP0+48R+VRHP)/SUMRP VREG1OUT - V*(VRP0+49R+VRHP)/SUMRP VREG1OUT - V*(VRP0+50R+VRHP)/SUMRP VREG1OUT - V*(VRP0+51R+VRHP)/SUMRP VREG1OUT - V*(VRP0+52R+VRHP)/SUMRP VREG1OUT - V*(VRP0+68R+VRHP)/SUMRP VREG1OUT - V*(VRP0+69R+VRHP)/SUMRP VREG1OUT - V*(VRP0+70R+VRHP)/SUMRP VREG1OUT - V*(VRP0+71R+VRHP)/SUMRP VREG1OUT - V*(VRP0+72R+VRHP)/SUMRP VREG1OUT - V*(VRP0+73R+VRHP)/SUMRP VREG1OUT - V*(VRP0+74R+VRHP)/SUMRP VREG1OUT - V*(VRP0+75R+VRHP)/SUMRP VREG1OUT - V*(VRP0+80R+VRHP)/SUMRP VREG1OUT - V*(VRP0+81R+VRHP)/SUMRP VREG1OUT - V*(VRP0+82R+VRHP)/SUMRP VREG1OUT - V*(VRP0+83R+VRHP)/SUMRP VREG1OUT - V*(VRP0+84R+VRHP)/SUMRP VREG1OUT - V*(VRP0+85R+VRHP)/SUMRP VREG1OUT - V*(VRP0+86R+VRHP)/SUMRP VREG1OUT - V*(VRP0+87R+VRHP)/SUMRP VREG1OUT - V*(VRP0+87R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+91R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+95R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+99R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+103R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+107R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+111R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+115R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+120R+VRHP+VRLP)/SUMRP Fine adjustment register value PKP0= 3'h0 PKP0= 3'h1 PKP0= 3'h2 PKP0= 3'h3 PKP0= 3'h4 PKP0= 3'h5 PKP0= 3'h6 PKP0= 3'h7 PKP1= 3'h0 PKP1= 3'h1 PKP1= 3'h2 PKP1= 3'h3 PKP1= 3'h4 PKP1= 3'h5 PKP1= 3'h6 PKP1= 3'h7 PKP2= 3'h0 PKP2= 3'h1 PKP2= 3'h2 PKP2= 3'h3 PKP2= 3'h4 PKP2= 3'h5 PKP2= 3'h6 PKP2= 3'h7 PKP3= 3'h0 PKP3= 3'h1 PKP3= 3'h2 PKP3= 3'h3 PKP3= 3'h4 PKP3= 3'h5 PKP3= 3'h6 PKP3= 3'h7 PKP4= 3'h0 PKP4= 3'h1 PKP4= 3'h2 PKP4= 3'h3 PKP4= 3'h4 PKP4= 3'h5 PKP4= 3'h6 PKP4= 3'h7 PKP5= 3'h0 PKP5= 3'h1 PKP5= 3'h2 PKP5= 3'h3 PKP5= 3'h4 PKP5= 3'h5 PKP5= 3'h6 PKP5= 3'h7 Reference voltage VINP0
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
SUMRP: Sum of positive ladder resistors =128R+VRHP+VRLP+VRP0+VRP1 V : Difference in electrical potential between VREG1OUT and VGS
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LGDP4531
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Table 87 Formula for calculating voltage (IPS=1)
Pin KVP0 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 KVP9 KVP10 www..comKVP11 KVP12 KVP13 KVP14 KVP15 KVP16 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP49 Formula VREG1OUT - V*VRP0/SUMRP VREG1OUT - V*(VRP0+5R)/SUMRP VREG1OUT - V*(VRP0+9R)/SUMRP VREG1OUT - V*(VRP0+13R)/SUMRP VREG1OUT - V*(VRP0+17R)/SUMRP VREG1OUT - V*(VRP0+21R)/SUMRP VREG1OUT - V*(VRP0+25R)/SUMRP VREG1OUT - V*(VRP0+29R)/SUMRP VREG1OUT - V*(VRP0+33R)/SUMRP VREG1OUT - V*(VRP0+33R+VRHP)/SUMRP VREG1OUT - V*(VRP0+34R+VRHP)/SUMRP VREG1OUT - V*(VRP0+35R+VRHP)/SUMRP VREG1OUT - V*(VRP0+36R+VRHP)/SUMRP VREG1OUT - V*(VRP0+37R+VRHP)/SUMRP VREG1OUT - V*(VRP0+38R+VRHP)/SUMRP VREG1OUT - V*(VRP0+39R+VRHP)/SUMRP VREG1OUT - V*(VRP0+40R+VRHP)/SUMRP VREG1OUT - V*(VRP0+61R+VRHP)/SUMRP VREG1OUT - V*(VRP0+62R+VRHP)/SUMRP VREG1OUT - V*(VRP0+63R+VRHP)/SUMRP VREG1OUT - V*(VRP0+64R+VRHP)/SUMRP VREG1OUT - V*(VRP0+65R+VRHP)/SUMRP VREG1OUT - V*(VRP0+66R+VRHP)/SUMRP VREG1OUT - V*(VRP0+67R+VRHP)/SUMRP VREG1OUT - V*(VRP0+68R+VRHP)/SUMRP VREG1OUT - V*(VRP0+100R+VRHP)/SUMRP VREG1OUT - V*(VRP0+101R+VRHP)/SUMRP VREG1OUT - V*(VRP0+102R+VRHP)/SUMRP VREG1OUT - V*(VRP0+103R+VRHP)/SUMRP VREG1OUT - V*(VRP0+104R+VRHP)/SUMRP VREG1OUT - V*(VRP0+105R+VRHP)/SUMRP VREG1OUT - V*(VRP0+106R+VRHP)/SUMRP VREG1OUT - V*(VRP0+107R+VRHP)/SUMRP VREG1OUT - V*(VRP0+128R+VRHP)/SUMRP VREG1OUT - V*(VRP0+129R+VRHP)/SUMRP VREG1OUT - V*(VRP0+130R+VRHP)/SUMRP VREG1OUT - V*(VRP0+131R+VRHP)/SUMRP VREG1OUT - V*(VRP0+132R+VRHP)/SUMRP VREG1OUT - V*(VRP0+133R+VRHP)/SUMRP VREG1OUT - V*(VRP0+134R+VRHP)/SUMRP VREG1OUT - V*(VRP0+135R+VRHP)/SUMRP VREG1OUT - V*(VRP0+135R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+139R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+143R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+147R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+151R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+155R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+159R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+163R+VRHP+VRLP)/SUMRP VREG1OUT - V*(VRP0+168R+VRHP+VRLP)/SUMRP Fine adjustment register value PKP0= 3'h0 PKP0= 3'h1 PKP0= 3'h2 PKP0= 3'h3 PKP0= 3'h4 PKP0= 3'h5 PKP0= 3'h6 PKP0= 3'h7 PKP1= 3'h0 PKP1= 3'h1 PKP1= 3'h2 PKP1= 3'h3 PKP1= 3'h4 PKP1= 3'h5 PKP1= 3'h6 PKP1= 3'h7 PKP2= 3'h0 PKP2= 3'h1 PKP2= 3'h2 PKP2= 3'h3 PKP2= 3'h4 PKP2= 3'h5 PKP2= 3'h6 PKP2= 3'h7 PKP3= 3'h0 PKP3= 3'h1 PKP3= 3'h2 PKP3= 3'h3 PKP3= 3'h4 PKP3= 3'h5 PKP3= 3'h6 PKP3= 3'h7 PKP4= 3'h0 PKP4= 3'h1 PKP4= 3'h2 PKP4= 3'h3 PKP4= 3'h4 PKP4= 3'h5 PKP4= 3'h6 PKP4= 3'h7 PKP5= 3'h0 PKP5= 3'h1 PKP5= 3'h2 PKP5= 3'h3 PKP5= 3'h4 PKP5= 3'h5 PKP5= 3'h6 PKP5= 3'h7 Reference voltage VINP0
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
SUMRP: Sum of positive ladder resistors =176R+VRHP+VRLP+VRP0+VRP1 V : Difference in electrical potential between VREG1OUT and VGS
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LGDP4531
Rev 1.15
Table 88 Formula for calculating voltage
Grayscale voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 www..com V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Formula VINP0 VINP1 VINP2+(VINP1-VINP2)*(30/48) VINP2+(VINP1-VINP2)*(23/48) VINP2+(VINP1-VINP2)*(16/48) VINP2+(VINP1-VINP2)*(12/48) VINP2+(VINP1-VINP2)*(8/48) VINP2+(VINP1-VINP2)*(4/48) VINP2 VINP3+(VINP2-VINP3)*(22/24) VINP3+(VINP2-VINP3)*(20/24) VINP3+(VINP2-VINP3)*(18/24) VINP3+(VINP2-VINP3)*(16/24) VINP3+(VINP2-VINP3)*(14/24) VINP3+(VINP2-VINP3)*(12/24) VINP3+(VINP2-VINP3)*(10/24) VINP3+(VINP2-VINP3)*(8/24) VINP3+(VINP2-VINP3)*(6/24) VINP3+(VINP2-VINP3)*(4/24) VINP3+(VINP2-VINP3)*(2/24) VINP3 VINP4+(VINP3-VINP4)*(22/23) VINP4+(VINP3-VINP4)*(21/23) VINP4+(VINP3-VINP4)*(20/23) VINP4+(VINP3-VINP4)*(19/23) VINP4+(VINP3-VINP4)*(18/23) VINP4+(VINP3-VINP4)*(17/23) VINP4+(VINP3-VINP4)*(16/23) VINP4+(VINP3-VINP4)*(15/23) VINP4+(VINP3-VINP4)*(14/23) VINP4+(VINP3-VINP4)*(13/23) VINP4+(VINP3-VINP4)*(12/23) Grayscale voltage V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Formula VINP4+(VINP3-VINP4)*(11/23) VINP4+(VINP3-VINP4)*(10/23) VINP4+(VINP3-VINP4)*(9/23) VINP4+(VINP3-VINP4)*(8/23) VINP4+(VINP3-VINP4)*(7/23) VINP4+(VINP3-VINP4)*(6/23) VINP4+(VINP3-VINP4)*(5/23) VINP4+(VINP3-VINP4)*(4/23) VINP4+(VINP3-VINP4)*(3/23) VINP4+(VINP3-VINP4)*(2/23) VINP4+(VINP3-VINP4)*(1/23) VINP4 VINP5+(VINP4-VINP5)*(22/24) VINP5+(VINP4-VINP5)*(20/24) VINP5+(VINP4-VINP5)*(18/24) VINP5+(VINP4-VINP5)*(16/24) VINP5+(VINP4-VINP5)*(14/24) VINP5+(VINP4-VINP5)*(12/24) VINP5+(VINP4-VINP5)*(10/24) VINP5+(VINP4-VINP5)*(8/24) VINP5+(VINP4-VINP5)*(6/24) VINP5+(VINP4-VINP5)*(4/24) VINP5+(VINP4-VINP5)*(2/24) VINP5 VINP6+(VINP5-VINP6)*(44/48) VINP6+(VINP5-VINP6)*(40/48) VINP6+(VINP5-VINP6)*(36/48) VINP6+(VINP5-VINP6)*(32/48) VINP6+(VINP5-VINP6)*(25/48) VINP6+(VINP5-VINP6)*(18/48) VINP6 VINP7
Note: Make sure DDVDH-V0 > 0.5V
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LGDP4531
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Relationship between RAM Data and Voltage Output Levels The relationship between RAM data and source output voltage levels is as follows..
Positive polarity V0
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V63
Negative polarity 111111 000000
RAM data (Common for each RGB pixel)
Figure 70 RAM data and the output voltage (REV = "1")
Sn
Negative polarity
Vcom
Positive polarity
Figure 71 Source output and Vcom
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LGDP4531
Rev 1.15
Power-supply Generating Circuit
The following figures show the configurations of liquid crystal drive voltage generating circuit of the LGDP4531.
Power supply circuit connection example 1 (Vci1 = VciOUT)
In the following example, the VciOUT level is adjusted internally with the VciOUT output circuit.
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Figure 72 Note: The wiring resistance between the schottky diode and GND/VGL must be 10Ohm or less.
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LGDP4531
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Power supply circuit connection example2 (Vci1 = Vci direct input)
In the following example, the electrical Vci is directly applied to Vci1. In this case, the VciOUT level cannot be adjusted internally but step-up operation becomes more effective
(1) (2) VREG1OUT
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VREG1 regulator
VCI (3) VCIOUT
Grayscale voltage generating circuit Source driver
S1-S720
VCI
VcomR VCI1 C11N (4) (5) C11P C12N
VCIOUT output circuit
Internal reference voltage generating circuit
VCOM
VCOM circuit Step-up circuit 1
VGH VGL
VCOML VCOMH
(17)
(18)
VCI (7) (6)
C12P VLOUT1 DDVDH
Gate driver
G1-G320
(8)
C13N C13P
(9)
C21N C21P
(10)
C22N C22P
VCC GND/RGND
(11) VCI (13) (12)
C23N C23P VLOUT2 VGH VLOUT3
Step-up circuit 2
VCILVL VCI AGND IOVCC IOGND VDD (19)
(14) (15)
VGL VLOUT4 VCL (16)
Figure 73 Note: 1. The wiring resistance between the schottky diode and GND/VGL must be 10Ohm or less. 2. When directly applying the Vci level to Vci1, set VC=3'h0.
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LGDP4531
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Specifications of Power-supply Circuit External Elements
The specifications of external elements connected to the power-supply circuit of the LGDP4531 are as follows. Table 89 Capacitor Capacitance 1uF www..com (B characteristics)
Voltage proof 6V
10V 25V Notes: 1. Check with the LC module. 2. The numbers in the parentheses corresponds to the numbers of the elements in Figure 72, Figure 73. Table 90 Schottky Diode Specification VF<0.4 V/20 mA@25, VR 30V
Pin Connection (1)VREG1OUT, (3)VciOUT, (4) C11N/P, (5) C12N/P, (8) C13N/P, (16) VLOUT4, (17) VCOML, (18) VCOMH, (19) VDD (6) VLOUT1, (9) C21N/P, (10) C22N/P, (11) C23N/P (12) VLOUT2, (14) VLOUT3
Pin Connection (7) Vci-DDVDH (15) GND-VGL (13) Vci-VGH
Table 91 Variable Resistor Specification >200k
Pin Connection (2) VcomR
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LGDP4531
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Voltage Setting Pattern Diagram
The pattern diagram of voltage setting and waveforms of the liquid crystal application voltages are as follows.
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Figure 74 Pattern Diagram for Voltage Setting Note Output voltages of DDVDH, VGH, VGL, and VCL drop from setting voltage(idea voltage) depending on the current consumption at output. (DDVDH - VREG1OUT) > 0.5V and (VCOML - VGL) > 0.5V are the relation to the actual voltage. When using the voltage in the large current consumption at the fast VCOM2 cycle( such as line-by-line inversion), check the voltage value
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LGDP4531
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Power Supply Instruction Setting
The following are the sequences for setting power supply ON/OFF. Make power supply ON/OFF settings according to the following sequences in Display ON/OFF, Standby set/exit, Sleep set/exit sequences.
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Power supply ON (Vcc, IOVcc, Vci)
Vcc, IOVcc, Vci simultaneously or Vcc -> IOVcc -> Vci
Normal display
DTE =1 D[1:0] = 3 GON = 1
Power ON reset 1 ms or more Start oscillation Stabilizing period for 10 ms or more oscillation circuit Set instruction to be issued before starting the power supply
Display OFF setting bits D[1:0] = 0, GON = 0, DTE = 0 PON = 0, VCOMG = 0
Display OFF sequence
Set instruction for turning off power supply
SAP[2:0]= 0 AP[2:0] = 0 VCOMG = 0 PON = 0 DK = 1
DC0[2:0] set, DC1[2:0] set, BT[3:0] set, RV[2:0] set VC[2:0] set, VRH[3:0] set, VCM[4:0] set, VDV[4:0] set
Set instructions for starting the power supply (1) Starting VGH 40 ms or more Set instructions for starting the power supply (2) Starting VGL 40 ms or more Set instructions for starting the power supply (3) Starting DDVDH & VCL Stabilizing period for oscillation circuit 70 ms or more Set instructions for other modes
SAP[2:0] set, AP[2:0] set, PON = 0
Turn the power supply off (Vcc, Vci, IOVcc)
PON = 1
Vci IOVcc Vcc GND Vci -> IOVcc -> Vcc Or Vcc, Vci, IOVcc simultaneously
DK = 0 VCOMG = 1
Display ON sequence
Figure 75
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LGDP4531
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Instruction Setting
The following are the sequences for various instruction settings with the LGDP4531. When making the following instruction settings, follow the respective sequences below.
Display ON/OFF sequence
Display OFF Display ON
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Display OFF (1) D[1:0] = 2, GON = 1, DTE = 1
LCD Power supply ON sequence
Display OFF (2) D[1:0] = 2, GON = 1, DTE = 0
Display ON (1) D[1:0] = 1, GON = 0, DTE = 0
Display OFF (3) D[1:0] = 2, GON = 0, DTE = 0
Display ON (2) D[1:0] = 1, GON = 1, DTE = 0
Display OFF (4) D[1:0] = 0, GON = 0, DTE = 0
Display ON (3) D[1:0] = 3, GON = 1, DTE = 0
LCD Power supply OFF sequence
Display ON (4) D[1:0] = 3, GON = 1, DTE = 1
Display OFF
Display ON
Figure 76
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LGDP4531
Rev 1.15
Sleep mode SET/EXIT sequences
Display OFF sequence
Sleep set (SLP = 1)
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Sleep release (SLP = 0)
Display ON sequence
Figure 77
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LGDP4531
Rev 1.15
Deep standby mode IN/EXIT sequences
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Figure 78
8-color mode setting
262,144 color to 8 color mode
262,144-color mode display
8 color to 262,144 color mode
8-color mode display
R07: COL = 1'h1
R07: COL = 1'h0
8-color mode display
262,144-color mode display
Figure 79
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LGDP4531
Rev 1.15
Parital Display setting
Full-screen display
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Partial display setting R80h : PTDP0 R81h : PTSA0 R82h : PTEA0 R83h : PTDP1 R84h : PTSA1 R85h : PTEA1
Base image display OFF Partial display ON R07h : BASEE =0 , PTDE = 1
8 color display, low power Consumption settings R07h : COL = 1 , R09h : PTS Set as required
Partial display
Base image display ON Partial display OFF R07h : BASEE =1 , PTDE = 0
Full-screen display
Figure 80
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LGDP4531
Rev 1.15
Absolute Maximum Ratings
Table 92 Item Power supply voltage (1) Power supply voltage (2) Power supply voltage (3) Power supply voltage (4) www..com Power supply voltage (5) Power supply voltage (6) Power supply voltage (7) Input voltage Operating temperature Storage temperature Symbol Vcc, IOVcc Vci - AGND DDVDH - AGND AGND - VCL DDVDH -VCL VGH - AGND AGND - VGL Vt Topr Tstg Unit V V V V V V V V C C value -0.3 ~ +4.5 -0.3 ~ +4.5 -0.3 ~ +8.0 -0.3 ~ +4.5 -0.3 ~ +8.0 -0.3 ~ +18 -0.3 ~ +18 -0.3~IOVcc+0.3 -40 ~ +85 -55 ~ +125 Notes 1, 2 1, 3 1, 4 1 1, 5 1, 6 1, 7 1 1, 8 1
Note 1) If used beyond the absolute maximum ratings, the LSI may permanently be damaged. It is strongly recommended to use the LSI at a condition within the electrical characteristics for normal operation. Exposure to a condition not within the electrical characteristics may affect device reliability. Note 2) Make sure (High) Vcc GND (Low), (High) IOVcc GND (Low). Note 3) Make sure (High) Vci GND (Low). Note 4) Make sure (High) DDVDH AGND (Low). Note 5) Make sure (High) DDVDH VCL (Low). Note 6) Make sure (High) VGH AGND (Low). Note 7) Make sure (High) AGND VGL (Low). Note 8) The DC/AC characteristics of die and wafer products is guaranteed at 85 .
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LGDP4531
Rev 1.15
Electrical Characteristics
DC Characteristics
Table 93
Item Input high-level voltage Input low-level voltage www..com Output high-level voltage (1) (DB17-0, SDO, FMARK) Output lowlevel voltage (1) (DB17-0, SDO, FMARK) I/O leakage current Current consumption : Deep standby mode Symbol VIH VIL VOH1 VOL1 IIi IST Unit V V V V A A Test condition IOVcc = 1.65 ~ 3.3V IOVcc = 1.65 ~ 3.3V IOVcc = 1.65 ~ 3.3V IOH = 0.1mA IOVcc = 1.65~ 3.3V IOL = 0.1mA Vin = 0 ~ IOVcc IOVcc = Vcc = Vci = 2.8V , Ta 25C -1 1 Min. 0.8IOVcc 0 0.8IOVcc 0.2IOVcc 1 10 Typ. Max. IOVcc 0.2IOVcc Notes 2,3 2,3 2 2 4 5
80-System Bus Interface Timing Characteristics (18/16-Bit Bus)
Table 94 See Figure 83 (Condition: IOVcc = 1.65 to 3.30V, Vcc = Vci = 2.50 to 3.30V)
Item Bus Cycle time Write "Low" level pulse width Read "Low" level pulse width Write "High" level pulse width Read "High" level pulse width Write/Read rise/fall time Setup time Address hold time Write data setup time Write data hold time Read data delay time Read data hold time Write (RS to CS*/ WR*) Read (RS to CS*/ RD*) tAH tDSW tH tDDR tDHR ns ns ns ns ns 5 Write Read Write Read Write Read Symbol tCYCW tCYCW PWLW PWLR PWHW PWHR
tWRr
Unit ns ns ns ns ns ns ns ns
Min. 50 250 25 150 25 100
Typ.
Max.
, tWRf
25 0 10 2 25 5 200
tAS
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LGDP4531
Rev 1.15
80-System Bus Interface Timing Characteristics (8/9-Bit Bus)
Table 95 See Figure 83 (Condition: IOVcc = 1.65 to 3.30V, Vcc = Vci = 2.50 to 3.30V)
Item Bus Cycle time Write "Low" level pulse width Read "Low" level pulse width Write "High" level pulse width www..comRead "High" level pulse width Write/Read rise/fall time Setup time Address hold time Write data setup time Write data hold time Read data delay time Read data hold time Write (RS to CS*/ WR*) Read (RS to CS*/ RD*) tAH tDSW tH tDDR tDHR ns ns ns ns ns 5 Write Read Write Read Write Read Symbol tCYCW tCYCW PWLW PWLR PWHW PWHR
tWRr
Unit ns ns ns ns ns ns ns ns
Min. 40 250 20 150 25 100
Typ.
Max.
, tWRf
25 0 10 2 25 5 200
tAS
Serial Peripheral Interface Timing Characteristics
Table 96 See Figure 84 (Condition: IOVcc = 1.65 to 3.30V, Vcc = Vci = 2.50 to 3.30V)
Item Serial clock cycle time Serial clock "High" level pulse width Serial clock "Low" level pulse width Serial clock rise/fall time Chip select setup time Chip select hold time Serial input data setup time Serial input data hold time Serial output data delay time Serial output data hold time Write (received) Read (transmitted) Write (received) Read (transmitted) Write (received) Read (transmitted) Symbol tSCYC tSCYC tSCH tSCH tSCL tSCL tscr , tscf tCSU tCH tSISU tSIH tSOD tSOH Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 5 20 60 30 30 130 Min. 50 250 25 150 25 100 20 Typ. Max.
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LGDP4531
Rev 1.15
RGB Interface Timing Characteristics
Table 97 See Figure 85 (18/16-bit I/F, IOVcc = 1.65 to 3.30V, Vcc = Vci = 2.50 to 3.30V)
Item VSYNC/HSYNC setup time ENABLE setup time ENABLE hold time DOTCLK "Low" level pulse width DOTCLK "High" level pulse width
www..comDOTCLK cycle time
Symbol tSYNCS tENS tENH PWDL PWDH tCYCD tPDS tPDH trgbr, trgbf
Unit ns ns ns ns ns ns ns ns ns
Min. 0 10 20 25 25 50 10 25
Typ.
Max.
Data setup time Data hold time DOTCLK, VSYNC, HSYNC rise/fall time
25
Reset Timing Characteristics
Table 98 See Figure 86 (Condition: IOVcc = 1.65 to 3.30V, Vcc = Vci = 2.50 to 3.30V)
Item Reset "Low" level width Reset rise time Symbol tRES trRES Unit ms us Min 1 Typ Max 10
LCD Driver Output Characteristics
Table 99 See Figure 87
Item Driver output delay time Symbol tDD Unit us Test Condition Vcc=3.0V, DDVDH=5.5V, VREG1OUT=5.0V, RC oscillation: fosc =2.5MHz (driving 320 lines), Ta=25C REV=0, SAP=010, AP=010, VRNx=5h'0, VRPx=5h'0, PKPx=3h'0, PKNx=3h'0, PRPx=3h'0, PRNx=3h'0, All pins undergo same changes from a same gray level. Time to reach 35mV during VCOM polarity inversion. Load resistance R=10k, Load capacitance C=20pF Min Typ T.B.D Max -
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LGDP4531
Rev 1.15
Notes to Electrical Characteristics
1. 2. The DC/AC electrical characteristics of bare die and wafer products are guaranteed at 85C. The following are the configurations of I pin, I/O pin, and O pin.
Pins:OSC1, TEST1 Pins: FMARK, SDO
Pins: RESET*, CS*, WR*/SCL, RD*, RS, IM[3:0], VSYNC, HSYNC, DOTCLK, ENABLE, SDI IOVcc
Vcc PMOS
IOVcc PMOS
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NMOS GND
NMOS GND
GND Pins: DB17- DB0 IOVcc
(Input circuit)
IOVcc GND (Output circuit: three states) Output enable Output data
GND
Figure 81 3. 4. 5. The TEST1 pin must be grounded (GND). The IM[3:0] pins must be fixed at either GND or the IOVcc level. This excludes currents though the output drive MOS. This excludes currents flowing through input/output units. Be sure that input levels are fixed to prevent increase in the transient current in input units when a CMOS input level takes medium range. While not accessing via interface pins, current consumption will not change whether the CS* pin is set to "High" or "Low". This is the case when an external oscillation resistor Rf is used.
OSC1 Oscillation frequency varies depending on the capacitances of OSC1, OSC2 pin. Make the wiring between OSC1 and OSC2 as short as possible. OSC2
6.
Figure 82
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LGDP4531
Rev 1.15
Table 100 RC Oscillation Frequency, Ta=25C
Oscillation Resistance (k) 5.1 5.6 6.8 8.2 10 12 15 www..com18 22 27 33 39 47 RC Oscillation Frequency : fosc (MHz) @ VCI = 2.8V , R15h=16'h0230 Min. Typ. Max. 5.9 6.9 8.0 5.6 6.6 7.6 5.0 5.9 6.8 4.4 5.2 6.0 3.9 4.6 5.2 3.4 4.0 4.6 2.8 3.3 3.8 2.4 2.9 3.3 2.1 2.4 2.8 1.7 2.0 2.3 1.5 1.7 2.0 1.2 1.5 1.7 1.0 1.2 1.4
Timing characteristic diagram
VIH VIH VIL tAS tAH
RS
VIL
VIH
VIH VIL
CS*
VIL
See Note 1)
PWLW, PWLR VIH VIL tWRr VIH
WR* RD*
tWRf
VIH VIL
PWLW, PWLR
tCYCW, tCYCR tDSW tH VIH VIL tDHR
See Note 2)
VIH VIL tDDR
DB0~DB17
Write data
See Note 2)
VOH1 VOL1
DB0~DB17
Read data
VOH1 VOL1
Note 1) PWLW and PWLR are defined by the overlap period when CS* is "Low" and WR* or RD* is "Low". Note 2) Unused DB pins must be fixed at "IOVCC" or "GND".
Figure 83 80-system bus interface operation
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LGDP4531
Rev 1.15
Start : S
End : P
CS*
VIL tSCYC tCSU tscf tSCH tSCL VIH VIL tSISU tSISH VIH VIH VIL VIL VIH tCH
VIH
tscr VIH VIL
SCL
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SDI
VIH
Input data
VIL tSOD VOH VOL VIL
Input data
tSOH VOH VOL
SDO
Output data
Output data
Figure 84 Serial Peripheral interface operation
trgbf trgbr
tSYNCS VIH VIL tENS VIH VIH VIL trgbf PWDL VIH VIL tCYCD tPDS VIH VIL VIH VIL tPDH tENH VIH VIL PWDH VIH VIL VIH VIL
HSYNC VSYNC
VIH VIL
ENABLE
trgbf VIH VIL
VIL
DOTCLK
PD17-0
Write data
VIH VIL
VIH VIL
Figure 85 RGB interface operation
trRES VIH VIL
tRES RESET* VIL
Figure 86 Reset operation
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LGDP4531
Rev 1.15
VCOM tDD S1-S720 target voltage 35mV
Figure 87 LCD driver outputs
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Revision History Rev. 1.13 1.14 1.14 1.14 1.15 1.15 1.15 1.15 Date 2007.04.28 2007.06.15 2007.06.15 2007.06.15 2007.07.03 2007.07.03 2007.07.03 2007.07.03 Revision Description p.150 Added RC-oscillation Frequecny : Table 100 p.22~27 Modified system interface : Figure 2, 3, 4, 6 p.33, 84 65k colors 262k colors ( 3-transfers mode ) : Table 7, Figure 25 p.119 Corrected alternating signal for frame inversion : Figure 60 p.7 Added descriptions of RS & FMARK pins when not in use : Table 1 p.126 PRP/N0 PRP/N1 : Figure 66 p.11 Revised the Pad Arrangement p.142 Erased the "wait clock" on sleep mode sequence : Figure 77 Revised by D.H. Kim S.H. Koh S.H. Koh S.H. Koh S.M. Kim D.H. Kim D.H. Kim D.H. Kim
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